In one embodiment, transceiver circuitry includes a first-in-first-out (FIFO) circuit and a control logic circuit. The FIFO circuit receives data signals based on a first clock frequency and outputs stored data signals based on a second clock frequency. The stored data signals are transmitted out of the FIFO circuit only in response to a difference between a value of a write pointer of the FIFO circuit and a value of a read pointer of the FIFO circuit exceeding an empty threshold limit of the FIFO circuit. The control logic circuit may be utilized to adjust the empty threshold limit of the FIFO circuit.

In a system and method for providing UI-to-UI asynchronous communication, a bridge is coupled to an asynchronous channel based bus that has at least one Galactic channel. The bridge receives each message on the Galactic channel, and converts each message from a channel message format used by the Galactic channel to a common message format. The bridge utilizes a socket to broadcast each converted message to, and receive messages from, the one or more other bridges. The bridge determines that a message received from the one or more other bridges is destined for the Galactic channel. The bridge converts the message into the channel message format used by the Galactic channel. The bridge distributes the converted message to the at least one Galactic channel.

An apparatus and method coupling a first and a second data bus comprising selectors for routing first bus egress lanes to egress memories, each egress memory coupled to one second bus egress lane, where the second bus has more egress lanes than the first. Each egress memory corresponds to one second bus egress lane. A first FSM selecting which first bus egress lane to load into each egress memory synchronous with the first bus clock. A second FSM outputting egress memory values to the second bus synchronous with the second bus clock. A set of ingress memories, each memory coupled to one second bus ingress lane and to an input of each ingress selector. A third FSM loading the ingress memories synchronous with the second bus clock. A fourth FSM selecting which ingress memory to route to each first bus ingress lane synchronous with the first bus clock.

In one embodiment, a method includes connecting, via a first interface of a controller card, a multiplexer of the controller card to a central processing unit (CPU) of the controller card. The method also includes connecting, via an interface of a first remote card, the multiplexer of the controller card to the first remote card. The method further includes interconnecting, by the multiplexer, the first interface of the controller card to the interface of the first remote card.

An industrial control system, such as a process control for use in a process plant, uses a hardware/software architecture that makes the system more reactive by making the system more resilient, responsive, and elastic. The industrial control system includes one or more distributed input/output (I/O) controller devices (BFN I/O controllers) which are coupled to field devices within a plant and provide direct or indirect access to the field devices for control and messaging purposes, one or more advanced function and computation nodes, and one or more user nodes coupled to the BFN I/O controllers via a network connection. The advanced function nodes store and execute virtual machines, devices, or entities, which decouples the hardware used in the control system from the software that functions on that hardware, making the system easier to scale, reconfigure, and change. Moreover, the industrial control system uses a self-describing data messaging scheme that provides both the data and a description of the data from a sender to a receiver, which enables different messaging protocols and data formats to be used in the control system, which also makes the system more open.

A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO.

A method includes receiving, by a storage driver associated with a storage controller and a corresponding storage array, a data structure associated with an I/O request from a host, wherein the data structure is indicative of a virtual address. A top layer and a RAID core layer of a RAID miniport driver execute asynchronously to perform pre-processing operations including generating a linked plurality of physical I/O (PIO) data structures in accordance with the virtual address and a RAID configuration of the storage array, and storing a pointer to the linked plurality of PIO data structures. A protocol layer of the RAID miniport driver may then be executed synchronously to transfer, in accordance with the linked plurality of PIO data structures, I/O data corresponding to the I/O request between the storage controller and the storage array. Interrupt operations may then be performed synchronously to indicate completion of the I/O request to the host.

An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

A method is described, for use in a data processing system, the system having a node and a communication link, wherein the communication link is coupled to the node. The method can comprise obtaining first digital signal information associated with a first signal, transmitting the first signal from the node to the communication link, receiving a second signal from the communication link at the node, and analyzing the second signal to obtain second digital signal information. The method can further include combining first digital signal information with second digital signal information and flagging a combination outside a predetermined condition space. Further, an apparatus, for use in the data processing system is described that can be operative to perform the method. A data processing system is also described.

A solid-state drive (SSD) for handling an Asynchronous Event Request (AER) command includes a command receiving circuit and a command management circuit. The command receiving circuit is configured to receive at least one command from at least one host. The command management circuit is configured to determine if the received at least one command from the at least one host is an AER command, store the AER command into an AER queue reserved for deferred AER command handling, if the received at least one command is the AER command, and generate a dummy response for the AER command and release resources occupied by the AER command.