A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO.

Methods and apparatus to identify a communication protocol being used in a process control system are disclosed. An example apparatus includes a process control device including a port to be in communication with a bus, the process control device to receive a first signal at the port and a second signal at the port, the process control device including a protocol detector to compare the first signal to reference communication protocols to identify the first signal as being associated with a first communication protocol, the protocol detector to compare the second signal to the reference communication protocols to identify the second signal as being associated with a second communication protocol, the first communication protocol being different than the second communication protocol, the processor to process the first signal based on the first communication protocol and the second signal based on the second communication protocol.

A system may include a digital sensor system including a sensor element and a digital interface. The digital interface may provide a wake-up signal based on a sensing action being performed by the sensor element after a predefined event is detected by the digital sensor system. The system may include a microcontroller to receive the wake-up signal provided by the digital interface, and wake from a sleep mode based on receiving the wake-up signal provided by the digital interface.

A method for sensing cable insertion into a connection installed in an electronic device. The electronic device includes a connector for inserting a cable, a first power manager configured to, when power is provided from the cable, output a signal corresponding to the power, a second power manager configured to transmit information instructing a supplying of the power to a processor, in accordance with the output of the signal, and the processor configured to control opening a path for the cable in accordance with the information.

A sound processing method for a sound device including at least a physical controller, connectable to a sound processing apparatus, the method including, control the physical controller to operate in a first mode to execute an assignable function in the sound device, and a second mode to execute a preassigned function in the sound processing apparatus in a state where the sound device is connected thereto, detecting whether the sound device is connected to the sound processing apparatus, and receiving a switching instruction to switch from the first mode to the second mode after detecting connection between the sound device and the sound processing apparatus.

An apparatus and method coupling a first and a second data bus comprising selectors for routing first bus egress lanes to egress memories, each egress memory coupled to one second bus egress lane, where the second bus has more egress lanes than the first. Each egress memory corresponds to one second bus egress lane. A first FSM selecting which first bus egress lane to load into each egress memory synchronous with the first bus clock. A second FSM outputting egress memory values to the second bus synchronous with the second bus clock. A set of ingress memories, each memory coupled to one second bus ingress lane and to an input of each ingress selector. A third FSM loading the ingress memories synchronous with the second bus clock. A fourth FSM selecting which ingress memory to route to each first bus ingress lane synchronous with the first bus clock.

A two-phase asynchronous transmission circuit for transmitting data over a wired interface according to a two-phase asynchronous protocol, the transmission circuit including: N data output lines, where N is an integer equal to 3 or more, wherein the transmission circuit is capable of transmitting N unique data symbols, each of the output lines being associated with a corresponding one of the N data symbols, and the transmission circuit is adapted to transmit each data symbol by applying a voltage transition to the corresponding output line independently of the voltage state of the other output lines.

A master device is provided which is coupled to a shared single line interrupt request (IRQ) bus and a control data bus. The master device group slave devices coupled to the shared single line IRQ bus into one or more groups, where each group is associated with a different IRQ signal. The master device then monitors the IRQ bus to ascertain when an IRQ signal is asserted by at least one slave device. The master device then identifies a group to with which the IRQ signal is associated. The slave devices for the identified group are then scanned or queried by the master device to ascertain which slave device asserted the IRQ signal on the IRQ bus. Each group uses a distinguishable IRQ signal to allow the master device to ascertain which group to query or scan.

The present invention provides an apparatus for expanding a serial communication port. The apparatus includes a first serial port, a second serial port and a processing and control module. The first serial port is used to transmit a first signal, and the second serial port is used to transmit a second signal. The processing and control module is coupled between the first serial port and the second serial port. The processing and control module includes a first serial bus host controller, a second serial bus host controller, a data forwarding unit and an expansion unit. The apparatus is connected between an electronic device and multiple peripheral devices, so that via the expansion unit, each peripheral device generates its own communication port on the electronic device.

An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.