A hybrid integrated circuit (HIC) with a high bandwidth, low-power, miniaturized, optically coupled data communication interface, the interface and an arrangement including the HIC. Active and passive components and integrated circuit (IC) chips may be mounted on an HIC substrate and collecting data. The HIC is smaller than one millimeter square and communicates data externally through a microLED (LED) array mounted on the HIC substrate and coupled to other HIC components. Each on LED consumes less than ten microwatts (10 W).

The present disclosure relates to a bus interface system including a bus line, master integrated circuitry (IC), and slave IC. The master IC is coupled to the bus line and configured to transmit the data signal to the slave IC through the bus line. The slave IC is coupled to the bus line so as to receive the data signal from the master IC and includes a supply capacitor, which is configured to store power from the data signal and provide a supply voltage to the slave IC. When the bus line is in the low state, the supply capacitor is isolated from the bus line. When the bus line is in the high state, the supply capacitor is allowed to extract power from the data signal on the bus line.

A method for managing communications involving a lockstep processing comprising at least a first processor and a second processor can include receiving, at a data synchronizer, a first signal from a first device. The method can also include receiving, at the data synchronizer, a second signal from a second device. In addition, the method can include determining, by the data synchronizer, whether the first signal is equal to the second signal. When the first signal is equal to the second signal, the method can include transmitting, by the data synchronizer, the first signal to the first processor and the second signal to the second processor. Specifically, in example embodiments, transmitting the first signal to the first processor can occur synchronously with transmitting the second signal to the second processor.

A communication control system includes a first processor, and a second processor coupled to the first processor via a plurality of communication lines and the second processor configured to select, for each packet of a plurality of packets, a communication line from the plurality of communication lines in specific order, and sequentially transmit each packet of the plurality of packets by using the selected communication line of the plurality of communication lines, wherein the first processor is configured to sequentially receive each packet of the plurality of packets by selecting a communication line from the plurality of communication lines in the specific order.

This application provides a spread spectrum clock negotiation method, and a peripheral component interconnect express device and system, to implement dynamic negotiation between a transmit end and a receive end on an SSC capability in the peripheral component interconnect express system. The method includes: A second PCIe device generates first indication information, where the first indication information is used to indicate whether the second PCIe device has a spread spectrum clock capability. The second PCIe device sends the first indication information to a first PCIe device. The first PCIe device determines, based on the first indication information, whether to perform spread spectrum clock on a reference clock of the first PCIe device.

A reconfigurable server includes improved bandwidth connection to adjacent servers and allows for improved access to near-memory storage and for an improved ability to provision resources for an adjacent server. The server includes processor array and a near-memory accelerator module that includes near-memory and the near-memory accelerator module helps provide sufficient bandwidth between the processor array and near-memory. A hardware plane module can be used to provide additional bandwidth and interconnectivity between adjacent servers and/or adjacent switches.

An open compute project (OCP) adapter card and a computer device are disclosed. The adapter card includes an OCP connector, a controller, a selector, and a motherboard connector. The OCP connector is configured to connect to an OCP network interface card (NIC). The controller is configured for bandwidth allocation, in-situ control and power-on/off control of the OCP NIC. The selector gates a single-homed host or a dual-homed host based on working mode configuration information stored in the controller. The motherboard connector is configured to connect to a motherboard device.

Disclosed in the present disclosure is an out-of-order data generation method. The method comprises: creating a plurality of threads; instructing all threads to acquire transmission permission in a manner of acquisition after random delay, determining, after any thread acquires the transmission permission, a thread as the current thread, and instructing the current thread to drive currently generated data and a corresponding data ID to an AXI bus for reading by a receiving end, so as to implement an out-of-order reading test on the basis of the data and corresponding data identifier that are read by the receiving end; and after sending, by the current thread, of the currently generated data and the corresponding data identifier ends, recycling the transmission permission, and returning to execute the step of instructing the all threads to acquire the transmission permission in the manner of acquisition after the random delay.

A programmable circuit is configured, including by selecting a plurality of target events to monitor in real time. A logical combination of the plurality of target events that correspond to a triggered preset state is specified. A corresponding action execution circuit module is associated with the triggered preset state. The target event monitoring module monitors the plurality of target events in real time and the preset state selecting module selects the corresponding action execution circuit module to run in the event the logical combination is satisfied. The corresponding action execution circuit module executes an action associated with enabling a reserved trigger function of a target solid state drive (SSD) memory.

Provided herein are systems and methods for performing dynamic adaption and correction for internal delays in devices connected to a common time-multiplexed bus. The methods allow devices to operate reliably at a higher bus frequency by correcting for inherent and unknown delays within the components and in the system by measuring the actual delays using multiple readings with the bus. Intrinsic noise and jitter are used to increase the precision of the measurements, thereby essentially using these uncertainties as self-dithering for increased measurement resolution. During adaption, delays may be adjusted in multiple step sizes to speed adaption time.