An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

Provided are a method and apparatus for method and apparatus for encoding registers in a memory module. A mode register command is sent to the memory module over a bus, initialization of the memory module before the bus to the memory module is trained for bus operations, to program one of a plurality of mode registers in the memory module, wherein the mode register command indicates one of the mode registers and includes data for the indicated mode register.

Embodiments include systems and methods for providing robust clock-skew-tolerant memory updating in high-speed memory circuits. For example, in each memory update interval, update of a pre-memory with un-validated update data begins when a potential match is detected between a tag memory and a key (whether according to a base clock or a delayed clock); but the update data is not considered valid (nor is it written out as such) until a determination is made according to the delayed clock. The un-validated update data can be written out from the pre-memory as validated update data for the memory update interval upon detection of a data valid indication generated from the delayed hit indication.

An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

A system, comprising: a plurality of modules, each module comprising a plurality of integrated circuits devices coupled to a module bus and a channel interface that communicates with a memory controller, at least a first module having a portion of its total module address space composed of first type memory cells having a first maximum access speed, and at least a second module having a portion of its total module address space composed of second type memory cells having a second maximum access speed slower than the first access speed.

A memory module, including a plurality of memory cells and a plurality of signal lines for communicating with a processing device. The memory module is configured such that following reception of a command and upon encountering a first condition while processing the command, the memory module limits a voltage on a first signal line of the plurality of signal lines to be no more than an intermediate voltage greater than voltage levels corresponding to a binary zero state and less than voltage levels corresponding to a binary one state for a period of time for indicating an occurrence of the first condition.

An apparatus is described. The apparatus includes a memory controller having an interface to communicate with a memory. The memory controller comprising logic circuitry to specify one of multiple possible write values to the memory during a write operation with multiple bits of a command that is sent on a command address bus that emanates from the interface. The memory to write any one of the possible write values into its storage cells while the memory interface is in a power saving state wherein the specified one write value is not articulated by the memory controller on a data bus of the interface as part of the write operation.

Techniques for command bus training to a memory device includes triggering a memory device to enter a first or a second command bus training mode, outputting a command/address (CA) pattern via a command bus and compressing a sampled CA pattern returned from the memory device based on whether the memory device was triggered to be in the first or the second command bus training mode.

The timing of the synchronous interface is controlled by a dock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.