Aspects include a computer-implemented method for initializing scannable and non-scannable latches from a clock buffer. The method includes receiving a clock signal; receiving control signals including a hold signal, a scan enable signal, and a non-scannable latch force signal; responsive to receiving a low input from the hold signal and the scan enable signal, outputting a high signal from a functional clock port on a next cycle; responsive to receiving a high input from the scan enable signal and a low input from the hold signal, outputting a high slave latch scan clock signal on the next cycle; responsive to receiving a high input from the hold signal and the scan enable signal, outputting a high master latch clock signal on the next clock cycle; and responsive to receiving a high input from the non-scannable latch force signal, outputting a low master latch clock signal on a current cycle.

A random access memory is connected to a processing unit through a memory interface. Access to the random access is memory is controlled by a process. The memory interface receives a request for access to the memory issued by the processing unit. In response to the request, the memory interface indicates to the processing unit that the memory is not available to receive another access request during a duration of unavailability. This duration can be differentiated depending on whether the received request is a write or read request. The value of the duration of unavailability associated with a write request and the value of the duration of unavailability associated with a read request are individually programmable independently of each other.

A memory module operable to communicate data with a memory controller via a memory bus. The memory module comprises memory devices and logic configurable to receive and register a set of input address and control signals associated with a read or write memory command and to output data transfer control signals. The memory module further comprises circuitry coupled between the memory bus and the memory devices. The circuitry is configurable to be in any of a plurality of states including a first state and a second state, and to transition from the first state to the second state in response to the data transfer control signals. The circuitry in the first state is configured to disable signal communication through the circuitry. The circuitry in the second state is configured to transfer the data signals associated with the read or write command in accordance with a transfer time budget of the memory module.

A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

A memory system includes a memory chip and a memory controller that controls the memory chip. In a write operation, the memory controller transfers a first timing signal synchronized with a first clock and first data synchronized with the first timing signal to the memory chip. In a read operation, the memory controller transfers a second timing signal synchronized with at least a second clock to the memory chip. The second clock has a frequency different from a frequency of the first clock. In the read operation, the memory chip generates a third timing signal synchronized with the second clock based on the second timing signal, and transfers the third timing signal and second data synchronized with the third timing signal to the memory controller.

In accordance with one embodiment, a computer-implemented method is provided, comprising the act of: configuring code or hardware to cause at least part of the hardware to operate as a double data rate (DDR) memory controller and to: produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of: at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

The reliability of a data communication link may be analyzed and otherwise maintained by collecting a two-dimensional array representing a functional data eye, and using a convolutional neural network to determine a score of the functional data eye. The determined score may be compared with a threshold, and an action may be initiated based on the result of the comparison.

A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.

The present invention provides a method performed by a secure digital (SD) card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode for initializing the SD card. The method includes: (a) after receiving a first supply voltage through a first voltage supply pin from a host coupled to the SD card, entering the SD mode if the SD card is not in the PCIe mode and a CMD0 command for entering the SD mode is received through a command pin from the host coupled to the SD card; and (b) after receiving the first supply voltage through the first voltage supply pin from the host coupled to the SD card, performing a PCIe linkup process if the SD card is not in the SD mode and a second supply voltage is received through a second voltage supply pin from the host coupled to the SD card. The SD card enters the PCIe mode if the PCIe linkup process succeeds.

A method may include receiving, at a storage device, a command for a data transfer between the storage device and a host, determining a specified data rate for the data transfer, and performing the data transfer between the storage device and the host based on the command, wherein the storage device may control the data transfer based on the specified data rate. The data transfer may include a peak portion and an idle portion. The method may further include controlling, at the storage device, a peak portion and an idle portion of the data transfer based on the specified data rate. The method may further include controlling, at the storage device, the data transfer based on a peak burst size. The specified data rate may be received from the host and/or determined by the storage device by monitoring one or more parameters of a data transfer.