A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

A connectivity has a first network (25) of signal-links interconnecting a large plurality of address-bearing, computing cells (20 and 22). Some of the links are selectable according to addresses hierarchically ordered along a recursive curve. Most of the address-designated links that form the network are switchably operable between cells such that a first selectable set of cells along one segment of the recursive curve form signal-routes to a second selectable set of cells, along a second segment. For receipt of instructions and for synchronisation, some segments have a switchable signal-path from one controlling cell of that segment. A second network (23) has signal-links interconnecting a plurality of processing cells (19 and 21) some of which control the loading of data into cells of the first network. The computing and processing cells have pairwise matching of addresses and are pairwise coterminous, which ensures that control of the connectivity by second network (23) is directed to localisably-selectable segments of first network (25).

A method of configuring a forwarding element that includes several message processing stages. The method identifies a first processing stage that starts processing a first header field of a message and a second processing stage that is the last message processing stage that processes the first header field. The method configures a field of a packet header container to store the first header field from the beginning of the first message processing stage. The method identifies a second header field used in a third processing stage after the second processing stage. The method configures a set of circuitries in the data plane to initialize the container field after the end of the second processing stage. The method configures the field of the container to store the second header field of the message after the end of the second processing stage and before the start of the third processing stage.

Methods, procedures, apparatuses, computer programs, computer-accessible mediums, processing arrangements and systems generally related to data multi-casting in a distributed processor architecture are described. Various implementations may include identifying a plurality of target instructions that are configured to receive a first message from a source; providing target routing instructions to the first message for each of the target instructions including selected information commonly shared by the target instructions; and, when two of the identified target instructions are located in different directions from one another relative to a router, replicating the first message and routing the replicated messages to each of the identified target instructions in the different directions. The providing target routing instructions may further comprise the selected information utilizing a subset of bits that is commonly shared by the target instructions and being identified as a left operand, right operand or predicate operand, and may include the selection of one of a plurality of multiple-instruction subsets of the target instructions.

For a logical switching element implemented across several managed switching elements, some embodiments provide a method that receives a packet for processing through a logical processing pipeline of the logical switching element. The method processes the packet through a first set of stages of the logical processing pipeline of the logical switching element. The method modifies a set of context tag values to indicate a logical output port of the logical switching element for the packet. The method forwards the packet to a managed switching element of the several managed switching elements based on the logical output port in the set of context tag values stored in the packet.

A flexible, scalable server is described. The server includes plural server nodes each server node including processor cores and switching circuitry configured to couple the processor to a network among the cores with the plurality of cores implementing networking functions within the compute nodes wherein the plurality of cores networking capabilities allow the cores to connect to each other, and to offer a single interface to a network coupled to the server.

A control system including several controllers for managing several switching elements. A first controller registers a second controller for receiving a notification when a data tuple changes in a network information base (NIB) storage of the first controller that stores data for managing a set of switching elements. The first controller changes the data tuple in the NIB. The first controller sends the notification to the second controller of the change to the data tuple in the NIB. The first and second controllers operate on two different computing devices. Each controller receives logical control plane data for specifying logical datapath sets and converts the logical control plane data to physical control plane data for enabling the switching elements to implement the logical datapath sets.

In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.

A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

An on-board network system includes a plurality of controllers connected to a bus, a detecting unit that detects an error that occurs, a measuring unit that measures a degree of error occurrence detected by the detecting unit, and a communication controller that reduces a communication speed and a communication data amount of at least one of the controllers from a first speed and a first data amount to a second speed and a second data amount, when the error occurrence degree becomes equal to or larger than a first degree. The communication controller reduces the communication speed and the communication data amount, such that a first communication time it takes for data to be transmitted at the first speed in the first data amount is longer than a second communication time it takes for data to be transmitted at the second speed in the second data amount.