Methods, systems, and apparatus, including an apparatus for generating clusters of building blocks of compute nodes using an optical network. In one aspect, a method includes receiving data specifying requested compute nodes for a computing workload. The data specifies a target arrangement of the nodes. A subset of building blocks of a superpod is selected. A logical arrangement of the subset of compute nodes that matches the target arrangement is determined. A workload cluster of compute nodes that includes the subset of the building blocks is generated. For each dimension of the workload cluster, respective routing data for two or more OCS switches for the dimension is configured. One-to-many switches are configured such that a second compute node of each segment of compute nodes is connected to a same OCS switch as a corresponding first compute node of a corresponding segment to which the second compute node is connected.

Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip (HSIC) interface are disclosed. In one exemplary embodiment, a device-initiated and host-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

A method of managing a network of calculation nodes interconnected by a plurality of interconnection devices, includes organizing the calculation nodes into groups of calculation nodes, for each group of calculation nodes, connecting the interconnection devices interconnecting the nodes of the group to a group management node, the management node being dedicated to the group of calculation nodes on each management node execution of an administration function by the implementation of independent management modules, each management module of a management node being able to communicate with the other management modules of the same management node.

A computing system framework and method for configuration thereof are provided. A plurality of processing modules are accessed. Each processing module includes a plurality of processing nodes and each processing node is associated with an intra-module port and an inter-module port. A plurality of intra-module networks are formed. Each intra-module network includes connections between at least a portion of the processing nodes in one of the processing modules via the associated intra-module ports. An enclosed shape of the processing modules is formed by connecting at one inter-module port on each processing module to one inter-module port on an adjacent processing modules. A cable is linked between one of the inter-module ports of one processing module of the enclosed shape to an inter-module port of another processing module of a different group of interconnected processing modules.

A connectivity has a first network (25) of signal-links interconnecting a large plurality of address-bearing, computing cells (20 and 22). Some of the links are selectable according to addresses hierarchically ordered along a recursive curve. Most of the address-designated links that form the network are switchably operable between cells such that a first selectable set of cells along one segment of the recursive curve form signal-routes to a second selectable set of cells, along a second segment. For receipt of instructions and for synchronisation, some segments have a switchable signal-path from one controlling cell of that segment. A second network (23) has signal-links interconnecting a plurality of processing cells (19 and 21) some of which control the loading of data into cells of the first network. The computing and processing cells have pairwise matching of addresses and are pairwise coterminous, which ensures that control of the connectivity by second network (23) is directed to localisably-selectable segments of first network (25).

Embodiments of the present invention provide a method, system and computer program product for the dynamic association of components in a multi-tier application to different layers of a corresponding multi-tier application infrastructure. In an embodiment of the invention, a method for dynamically associating components in a multi-tier application to different layers of a corresponding multi-tier application infrastructure includes defining in memory of a host computing system a pattern that has an inventory of components of a multi-tier application. The method also includes associating each of the components with a corresponding tier label for an n-tier architecture. The method yet further includes loading the pattern into a pattern engine. Finally, the method includes deploying by the pattern engine each component of the pattern to a layer of the n-tier architecture corresponding to a tier label associated with the component.

Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.

Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.

A computing system framework and method for configuration thereof are provided. A plurality of processing modules is accessed. Each processing module includes a plurality of processing nodes and each processing node is associated with an intramodule port and an intermodule port. The processing modules are connected in a ring via intermodule connections between at least a portion of the intermodule ports of the processing modules. A network switch is arranged in a center of the ring of processing modules and connections are formed between the network switch and at least one of the processing modules by connecting every Sth processing module to the network switch, connecting every Sth and Sth1 processing modules to the network switch, or by connecting every Sth and Sthr processing modules to the network switch. S is a number of steps between the processing modules.

A plurality of software programmable processors is disclosed. The software programmable processors are controlled by rotating circular buffers. A first processor and a second processor within the plurality of software programmable processors are individually programmable. The first processor within the plurality of software programmable processors is coupled to neighbor processors within the plurality of software programmable processors. The first processor sends and receives data from the neighbor processors. The first processor and the second processor are configured to operate on a common instruction cycle. An output of the first processor from a first instruction cycle is an input to the second processor on a subsequent instruction cycle.