Systems and methods implemented in firmware and hardware domains may include writing by the firmware domain configuration information to a memory for a plurality of passes of hardware processing, programming by the hardware domain configuration registers with the configuration information retrieved from the memory, and processing by the hardware domain the plurality of passes in accordance with the configuration information programmed in the configuration registers. The configuration registers may be programmed after the configuration information are written to the memory.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

Embodiments herein describe a SoC that includes a programmable NoC that can be reconfigured to support different interface communication protocols. In one embodiment, the NoC includes ingress and egress logic blocks which permit hardware elements in the SoC (e.g., processors, memory, programmable logic blocks, etc.) to transmit and receive data using the NoC. The ingress and egress logic blocks may first be configured to support a particular communication protocol for interfacing with the hardware elements. However, at a later time, the user may wish to reconfigure the ingress and egress logic blocks to support a different communication protocol. In response, the SoC can reconfigure the NoC such that the ingress and egress logic blocks support the new communication protocol used by the hardware elements. In this manner, the programmable NoC can support multiple communication protocols used to interface with other hardware elements in the SoC.

A graphics processing pipeline includes a rasteriser, an early culling tester, a renderer, a late culling tester, and a culling test data buffer that stores data values for use by the early and late culling testers. The testing of fragments by the early and late culling testers is controlled in accordance with a first set of state information indicative of when a culling test operation to be used to determine whether to cull the fragments is to be performed, and a second set of state information indicative of when to determine whether to update the culling test data buffer with data for the fragments based on a culling test operation, allocated to the fragments.

Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

A technology is described for a programmable compute architecture with clusters of floating point units (FPUs), a random-access-memory (RAM), and a plurality of configurable logic blocks (CLBs) defining a data plane and a limited instruction set central processing unit (CPU) communicating in the cluster with the FPUs, the RAM, and the CLBs as a control plane. The CPU can control branching and/or looping the FPUs and the CLBs.

Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

In one embodiment, a processor includes: a plurality of cores to execute instructions and a non-volatile storage coupled to the plurality of cores to store identification information regarding the plurality of cores, the identification information to identify, for each of the plurality of cores, the core as an assured core or an opportunistic core. The processor is specified with a first subset of the plurality of cores comprising assured cores and a second subset of the plurality of cores comprising opportunistic cores, and is to execute, within a specified power budget and a specified thermal budget, a specified workload on the first subset of the plurality of cores at a first performance level. Other embodiments are described and claimed.