A display is provided that includes an array of display pixels that receive data signals from display driver circuitry and that receive control signals from gate driver circuitry. The gate driver circuitry may include a chain of row driver circuits. Each row driver circuit in the chain of row driver circuits may include a master driver stage, a slave driver stage, and associated control circuitry configured to receive a clock signal and a pulse signal from a preceding row driver in the chain. The master driver stage may be biased using fixed nominal power supply voltages, whereas the slave driver stage may be biased using dynamically adjustable power supply voltages that are optionally reduced relative to that of the nominal power supply voltages. One or more of the master and slave driver stages may be a bootstrapping driver stage having a bootstrapping capacitor.

A display apparatus includes pixels and a gate driver. The pixels include N pixels arranged in order, and N is a positive integer greater than or equal to 2. The N pixels include a p.sup.th pixel and a q.sup.th pixel, wherein p is an odd number less than or equal to N and a positive integer, and q is an even number less than or equal to N and a positive integer. The gate driver is electrically connected to a scan line of the p.sup.th pixel and receives a first start signal to generate a first gate pulse signal in a first sub-frame interval of a frame interval. The gate driver is electrically connected to a scan line of the q.sup.th pixel and receives a second start signal to generate a second gate pulse signal in a second sub-frame interval of the frame interval following the first sub-frame interval.

A display apparatus includes pixels and a gate driver. The pixels include N pixels arranged in order, and N is a positive integer greater than or equal to 2. The N pixels include a p.sup.th pixel and a q.sup.th pixel, wherein p is an odd number less than or equal to N and a positive integer, and q is an even number less than or equal to N and a positive integer. The gate driver is electrically connected to a scan line of the p.sup.th pixel and receives a first start signal to generate a first gate pulse signal in a first sub-frame interval of a frame interval. The gate driver is electrically connected to a scan line of the q.sup.th pixel and receives a second start signal to generate a second gate pulse signal in a second sub-frame interval of the frame interval following the first sub-frame interval.

A display device includes: a substrate including at least two layers; a driving circuit on the substrate; a pixel electrode connected to the driving circuit; a common electrode on the pixel electrode; a display layer between the pixel electrode and the common electrode; and a thermoelectric element located between the at least two layers of the substrate.

A display device includes: a substrate including at least two layers; a driving circuit on the substrate; a pixel electrode connected to the driving circuit; a common electrode on the pixel electrode; a display layer between the pixel electrode and the common electrode; and a thermoelectric element located between the at least two layers of the substrate.

A common electrode driver includes an inverting amplifier including a first resistor, a second resistor, and an operational amplifier, and a resistance ratio adjustment circuit that adjusts, in accordance with a length of one horizontal scan period, a resistance ratio being a ratio of a resistance value of the second resistor to a resistance value of the first resistor. A feedback voltage is provided to one end of the first resistor. The resistance ratio adjustment circuit sets the resistance ratio when second driving is performed, in which a length of one horizontal scan period is a second time longer than a first time, to be smaller than the resistance ratio when first driving is performed, in which a length of one horizontal scan period is the first time.

A method of driving a display panel is disclosed. In one aspect, the display panel includes a plurality of pixels arranged in odd and even rows and a plurality of odd and even gate lines respectively connected to the pixels of the corresponding odd and even rows. The method includes outputting odd gate signals to the odd numbered gate lines during two consecutive subframes and outputting even gate signals to the even numbered gate lines during two consecutive subframes. A frame is divided into two subframes.

A method of driving a display panel is disclosed. In one aspect, the display panel includes a plurality of pixels arranged in odd and even rows and a plurality of odd and even gate lines respectively connected to the pixels of the corresponding odd and even rows. The method includes outputting odd gate signals to the odd numbered gate lines during two consecutive subframes and outputting even gate signals to the even numbered gate lines during two consecutive subframes. A frame is divided into two subframes.

A display controller disposed in a display device that includes a flash memory and an integrated circuit is provided. The flash memory stores display device information of the display device. The integrated circuit includes a first and a second power conversion circuit and an accessing circuit. The first power conversion circuit converts an external power received from an external power adapter to a power in a first power domain. The second power conversion circuit converts a host power received from a host to the power of a second power domain and outputs the power to a flash memory such that the flash memory operates accordingly. The accessing circuit operates according to the power of the second power domain to access and transmit the display device information from the flash memory to the host when the first power conversion circuit is not in operation.

A display controller disposed in a display device that includes a flash memory and an integrated circuit is provided. The flash memory stores display device information of the display device. The integrated circuit includes a first and a second power conversion circuit and an accessing circuit. The first power conversion circuit converts an external power received from an external power adapter to a power in a first power domain. The second power conversion circuit converts a host power received from a host to the power of a second power domain and outputs the power to a flash memory such that the flash memory operates accordingly. The accessing circuit operates according to the power of the second power domain to access and transmit the display device information from the flash memory to the host when the first power conversion circuit is not in operation.