A shift register includes an input sub-circuit, a first noise reduction sub-circuit, and a first pull-down sub-circuit. The first noise reduction sub-circuit is coupled to the pull-up node, the first pull-down node and a first voltage signal terminal, and is configured to transmit a first voltage signal to the pull-up node under control of the first pull-down node; the input sub-circuit is coupled to the pull-up node and a signal input terminal, and is configured to transmit an input signal to the pull-up node in response to the input signal; the first pull-down sub-circuit is coupled to the signal input terminal, the first pull-down node and the first voltage signal terminal, and is configured to transmit the first voltage signal to the first pull-down node in response to the input signal, so that the first noise reduction sub-circuit stops transmitting the first voltage signal to the pull-up node.

The disclosure provides a display device and another display device. The display device includes a display panel. The display panel has a functional display area. The functional display area includes a pixel. The pixel includes a white pixel and multiple display pixels. The display pixels surround at least a part of the white pixel, and the white pixel includes a pixel electrode. The another display device includes another display panel. The another display panel has a functional display area, and the functional display area includes a pixel and a signal line. The pixel includes a white pixel and multiple display pixels. The signal line includes a branch, and the branch is electrically connected to one of the display pixels. The display device and the another display device of the disclosure is capable of reducing the problem of diffraction or having a better optical sensing effect.

A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.

A gate driver for a display device includes: a clock signal line to transfer a clock signal; and a plurality of stages to sequentially output a gate signal based upon the clock signal in response to a carry signal. The plurality of stages include a plurality of thin film transistors, and at least one of the plurality of thin film transistors includes a thin film transistor including an oxide semiconductor. The at least one thin film transistor includes a first gate electrode and a second gate electrode disposed in different layers, the oxide semiconductor is disposed between the first gate electrode and the second gate electrode, and the first gate electrode and the second gate electrode are connected to receive a common voltage signal.

Disclosed are a gate driving circuit and a display device. According to the gate driving circuit, in every five adjacent shift registers, the output control end of the first shift register is electrically connected to the input signal end of the fifth shift register; in every six adjacent shift registers, the output control end of the sixth shift register is electrically connected to the reset signal end of the first shift register. In the gate driving circuit of a cascade structure provided by the present disclosure, there are fewer cascade signal lines, thereby saving space, further implementing the narrow bezel of a display device; in addition, for the gate driving circuit of a cascade structure provided by the present disclosure, the signal provided by an external circuit board can be more flexible, even if a display product is manufactured, the pulse width of a clock signal can be adjusted by means of the external circuit board, thereby adjusting the high-level width of a gate signal output by a gate signal output end, and the flexibility is high.

A display panel, a display device and a driving method. The display panel includes a display region and a peripheral region. The display region includes a subpixel unit array having a plurality of rows and a plurality of columns of subpixel units, and the peripheral region includes a gate drive circuit. The display region further includes a plurality of gate lines and a plurality of data lines. Each subpixel unit is driven by a scanning signal provided by one gate and a data signal provided by one data line, and a same data line is connected with at least two subpixel units which are not adjacent to each other and have a same color. The gate drive circuit includes a plurality of shift register units, and the plurality of gate lines are electrically connected with the plurality of shift register units in a one-to-one correspondence in order.

The present disclosure provides a pixel structure, a method of driving the same and a display device. The pixel structure includes gate lines, data lines, and a plurality of subpixels arranged in an array form. Subpixels in each row correspond to two gate lines. Each data line corresponds to the subpixels in two adjacent columns, and each data line is arranged between the two adjacent columns of subpixels. Among the subpixels in each row, three adjacent subpixels are in different colors and forms a complete pixel unit. Among the subpixels in each column, three adjacent subpixels are in different colors and forms the complete pixel unit. Among the subpixels in two adjacent columns, the subpixels in two adjacent rows form two complete pixel units each including three subpixels, and two of the three subpixels are shared by the two pixel unit.

A power management integrated circuit includes a flip-flop circuit configured to perform a logic operation on a start clock signal which sets a driving start time point of a gate driving circuit and an on-clock signal which sets an output start time point of the gate driving circuit; a first AND gate circuit configured to receive one among output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate start signal; and a second AND gate circuit configured to receive the other of the output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate reset signal.

A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor. In the second transistor, a first terminal is electrically connected to the first wiring, a second terminal is electrically connected to a sixth wiring, a gate is electrically connected to the first circuit and a gate of the third transistor. A second terminal of the third transistor is electrically connected to the sixth wiring. The first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.

The present application provides a gate driving unit circuit and a method of driving the same, a gate driving circuit and a display apparatus. The gate driving unit circuit includes a shift register and a plurality of driving signal output sub-circuits. Each driving signal output sub-circuit corresponds to one of gate lines on an array substrate, is coupled to a first power supply terminal and a signal output terminal of the shift register, and also coupled to a corresponding one of driving scan signal lines. Each driving signal output sub-circuit is configured to output, under the control of a signal output by the signal output terminal of the shift register, a driving scan signal provided by the corresponding driving scan signal line or an OFF voltage provided by the first power supply terminal to the corresponding gate line.