Disclosed are a drive circuit, an array substrate and a display panel. The first signal line is for receiving and transmitting the first reset control signal after the display of the current frame ends. First ends of the first thin film transistor and the second thin film transistor are connected to the first signal line. Second ends of the first thin film transistor and the second thin film transistor are connected to the second signal line. Third ends of the first thin film transistor and the second thin film transistor are connected to the controlled end and output end of the output module, respectively. The first thin film transistor and the second thin film transistor are for outputting the DC signal to the controlled end and the output end of the output module, respectively, upon receiving the first reset control signal, to reset the output module.

Disclosed is a driving circuit including an input circuit, a first output circuit, a second output circuit and a pull-down circuit. Control terminals of the first output circuit and the second output circuit are connected with an output terminal of the input circuit and receive a control signal from the input circuit, and output terminals of the first output circuit and the second output circuit are connected with the pull-down circuit and receive a pull-down signal. Thus, two stages of driving signals output by one stage driving circuit is realized. As compared with the existing architecture under which the two stage driving circuit is needed to output two stages of driving signals, one input circuit and one pull-down circuit are removed. This application also discloses a four-stage driving circuit and a display panel. The number of used components is reduced, and the frame of the display product is narrowed.

The present application provides a GOA circuit and a display panel. In the GOA circuit, one of two GOA units of a same stage in GOA sub circuits at left and right sides of the display panel is deployed only with an all-on module and the other one of the two GOA units is deployed only with an all-off module. In such a way, both the number of the all-on modules and the number of the all-off modules required in the GOA unit are halved, thereby reducing the area occupied by the GOA circuit. It is beneficial for realizing a display panel with a narrow bezel.

Disclosed is an array substrate, a display panel, and a display apparatus, and belongs to the field of displays. The array substrate includes: a base substrate, including a display region and a peripheral region surrounding the display region; a plurality of clock lines, disposed on the base substrate and in the peripheral region, wherein the clock lines extend in a first direction; a plurality of clock leads, disposed on the base substrate and in the peripheral region, wherein the clock leads extend in a second direction, and the first direction intersects with the second direction; a plurality of shift register units, disposed on the base substrate and in the peripheral region, wherein the shift register units are connected to the clock lines by the clock leads; and compensation capacitor plates, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plates are connected to the clock leads, the compensation capacitor plates and the clock leads are in different layers, and an area of the compensation capacitor plate is negatively correlated with a length of a clock lead connected to the compensation capacitor plate.

The present disclosure provides a gate driving unit, a gate driving method, a gate driving circuit and a display device. The gate driving unit includes a first clock signal end, a second clock signal end, a third clock signal end, a fourth clock signal end, a first output node control circuitry, a second output node control circuitry, a first control node control circuitry and an output circuitry. According to the present disclosure, it is able to provide a gate driving signal for an N-type transistor in an LTPO pixel circuit, and reduce the number of transistors, thereby to provide a narrow bezel.

A charge sharing circuit, a charge sharing method, a display driving module and a display device are provided. The charge sharing circuit includes a control unit and a switch unit. The control unit is electrically connected to first output control ends of two clock signal generation units, and configured to provide, when a first output module controls to not output a first voltage signal under the control of a first output control signal, an on control signal to the switch unit through a control signal output end. The switch unit is configured to control clock signal output ends of the two clock signal generation units to be electrically connected to each other under the control of the on control signal.

A shift register unit and a driving method thereof, a gate drive circuit and a display device. The shift register unit includes a first input circuit, an output circuit and a first output pull-down circuit. The first input circuit is configured to charge a pull-up node in response to a first clock signal and reset the pull-up node in response to the first clock signal; the output circuit is configured to output a second clock signal to an output terminal under a control of a level of the pull-up node; the first output pull-down circuit is configured to denoise the output in response to a third clock signal.

A liquid crystal display apparatus switches modes from a normal display mode to a stop preparation mode when a main power source voltage drops. In the display mode, a gate drive circuit sequentially applies a first gate-on pulse to gate bus lines so as to select pixel rows sequentially, and applies a second gate-on pulse to buffer capacitor scanning lines, each of which is associated with a pixel row selected by the first gate-on pulse, during a period that does not overlap a period during which the first gate-on pulse is applied, and a source drive circuit applies a display signal voltage to source bus lines. In the stop preparation mode, the gate drive circuit sequentially applies the first gate-on pulse to the gate bus lines so as to select the pixel rows sequentially, and applies the second gate-on pulse to the buffer capacitor scanning lines, each of which is associated with the pixel row selected by the first gate-on pulse, during a period that at least partially overlaps a period during which the first gate-on pulse is applied, and the source drive circuit applies 0 V to the source bus lines.

Circuit and method for preventing screen flickering, a drive circuit for a display panel, and a display apparatus are provided, relating to the field of display technology. The circuit for preventing screen flickering includes a control sub-circuit configured to control a gate drive circuit of the display panel to output a gate cut-off level during a power-on period of the display panel. The gate drive circuit of the display panel is controlled to output the gate cut-off level during the power-on period, the gate cut-off level is provided to gate lines of the display panel such that TFTs connected to the gate lines are in cut-off state during the power-on period.

A video display includes a display panel with gate drivers and source drivers. Each of said the source drivers is arranged to receive a discrete-time continuous-amplitude signal representing a video stream over a transmission medium and to decode the signal using demodulation to produce a plurality of samples for output on outputs of the source drivers. At least one of the source drivers is arranged to extract a gate driver timing control signal from the signal and to output the gate driver control signal to the gate drivers in order to synchronize the gate drivers with outputs of the source drives, whereby the video stream is displayed on the display panel of the display unit.