Patent classifications
G09G3/3674
DISPLAY DEVICE
A display device includes a display substrate, a plurality of source drive circuit elements, gate drive circuits, and a plurality of gate connection lines. The plurality of gate connection lines pass through inter-element regions between the source drive circuit elements in plan view, and pass through mounting regions. Gate terminals connected to the gate connection lines are formed at positions facing the inter-element regions in a direction from the inter-element regions toward an FPC (Y2 direction).
SHIFT REGISTER CIRCUIT
A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
SHIFT REGISTER UNIT, CIRCUIT STRUCTURE, GATE DRIVE CIRCUIT, DRIVE CIRCUIT AND DISPLAY DEVICE
A shift register unit, a circuit structure, a gate drive circuit, a drive circuit and a display device are provided. A shift register unit includes a substrate and an input circuit, a reset circuit, a first output circuit, a first output terminal, a first connection conductive portion connecting both the input circuit and the reset circuit, a second connection conductive portion connecting both the reset circuit and the first output circuit, and a third connection conductive portion connecting both the first output circuit and the first output terminal, all of which are on the substrate.
Shift Register, Gate Driving Circuit, Display Apparatus and Driving Method
Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.
Touch display device, driving circuit, and driving method
A touch display device, a driving circuit, and a driving method are provided. An image defect which occurs when display driving and touch driving are simultaneously executed can be reduced by performing control such that a voltage level of a touch electrode driving signal (TDS) varies in a section other than a high-level period (Pon) of an ON-clock signal (ON_CLK) and/or a high-level period (Poff) of an OFF-clock signal (OFF_CLK).
Display device and method of driving the same
A display device includes a display panel displaying an image, a scan driver configured to apply scan signals to the display panel, and a power supply configured to apply a gate high voltage and a gate low voltage to the scan driver. The scan driver discharges the display panel based on a second gate high voltage lower than the gate high voltage during a discharging operation of the display panel.
METHOD FOR DRIVING DISPLAY DEVICE
To suppress degradation of a transistor. A method for driving a liquid crystal display device has a first period and a second period. In the first period, a first transistor and a second transistor are alternately turned on and off repeatedly, and a third transistor and a fourth transistor are turned off. In the second period, the first transistor and the second transistor are turned off, and the third transistor and the fourth transistor are alternately turned on and off repeatedly. Accordingly, the time during which the transistor is on can be reduced, so that degradation of characteristics of the transistor can be suppressed.
GOA CIRCUIT AND DISPLAY PANEL
In a GOA circuit and a display panel provided by embodiments of the present application, a reset module is provided in each level of GOA units, so that each level of the GOA units can output a high potential before an end of a frame, all gates in a display area are turned on, and a charge of all pixels in the display area is discharged; after that, each level of the GOA units outputs a low potential, and all of the gates in the display area are set to the low potential.
Touch Display Device
A touch display device is disclosed that . has enhanced touch sensing accuracy in its periphery area. The touch display device comprises: a display panel including data lines, gate lines, subpixels, and touch electrodes that overlap a subpixel; a touch power circuit configured to generate and output a signal pulse width that is modulated; a gate driving circuit configured to supply a scan signal to the gate lines; a display controller configured to output a gate driving circuit control signal that controls controlling a driving timing of the gate driving circuit; a first line in a non-display area of the display panel that receives the gate driving circuit control signal; and a second line in the non-display area that receives the signal pulse width, wherein a width of the second line is larger than a width of the first line.
DISPLAY DEVICE
A display device can include a left ripple transistor provided in a left stage to remove ripple occurring in a Q node of the left stage, and a right ripple transistor provided in a right stage to remove ripple occurring in a Q node of the right stage. These ripple transistors perform an on operation and an off operation repeatedly and simultaneously.