Disclosed is a gate driving circuit comprising a plurality of stage circuits dependently connected to each other and configured to output ‘j’ output signals ('j′ is an integer of 2 or more), wherein each of the plurality of stage circuits includes a logic controller for controlling a voltage of each of first and second nodes, and an output circuit unit for outputting each of ‘j’ clock signals as the ‘j’ output signal in response to the voltage of the first node, wherein the output circuit unit includes ‘j’ output buffers for outputting each of the ‘j’ clock signals as the ‘j’ output signal through an output node in response to the voltage of the first node, and a capacitor prepared between the first node and the output node of some of the ‘j’ output buffers.

A display apparatus includes a first substrate, a first dummy substrate on the first substrate, and a second dummy substrate extending from the first dummy substrate and bent. The second dummy substrate is on different side surfaces of the first substrate in a first direction. The display apparatus also includes a plurality of pixels on the first dummy substrate, a gate driver on the second dummy substrate and connected to the pixels, and a data driver connected to one side of the first dummy substrate in a second direction crossing the first direction and connected to the pixels.

The present disclosure provides a shift resister unit, a gate driving circuit, a display device, and a method for controlling a shift register unit. The shift register unit incudes a first input sub-circuit, a first output sub-circuit, a first reset sub-circuit, a second input sub-circuit, and a third input sub-circuit. The first input sub-circuit is configured to change a potential of a first node in a first phase. The first output sub-circuit is configured to output a gate driving signal in the first phase and output a compensation driving signal in a second phase. The first reset sub-circuit is configured to reset the first node. The second input sub-circuit is configured to change a potential of a second node in the first phase and maintain the potential of the second node. The third input sub-circuit is configured to change the potential of the first node in the second phase.

An emission control driver includes a plurality of stages. Each stage includes three circuit blocks and two output transistors. A first circuit block generates first and second control signals based on a first clock signal and a start signal or carry signal. A second circuit block controls the voltage level of the first control signal based on the first control signal and a second clock signal. A third circuit block generates a third control signal based on the second control signal and the second clock signal. The first output transistor outputs a first voltage as an emission control signal based on the first control signal. A second output transistor outputs a second voltage as the emission control signal based on the third control signal. The second circuit block maintains the voltage level of the first control signal while the first output transistor is turned off.

A driving method and device for a shift register. In a data refreshing phase, loading an input signal having a pulse level to an input signal end, loading a control clock pulse signal to a control clock signal end, loading a noise reduction clock pulse signal to a noise reduction clock signal end, controlling a cascade signal end of the shift register to output a cascade signal having a pulse level, and controlling a drive signal end of the shift register to output a drive signal having a pulse level; in a data holding phase, loading a fixed voltage signal to the input signal end, loading a first set signal to the control clock signal end, loading a second set signal to the noise reduction clock signal end, controlling the cascade signal end to output a fixed voltage signal having a second level.

A display panel of the present application is disclosed. The display panel includes a GOA circuit, a plurality of clock main lines on a side of the GOA circuit, and a plurality of clock branch lines connected to each of the corresponding clock main lines, respectively. By providing the different first protrusion components and second protrusion components in the corresponding clock branch lines, the equivalent impedance of these clock branch lines can be adjusted to be equal. By providing the bridge components with different areas in the corresponding clock branch lines, the equivalent capacitive reactance of these clock branch lines can be adjusted to be equal.

A display device comprises: a panel driving unit comprising panel driving circuitry; a display panel including a plurality of pixels; and a processor configured to control the panel driving unit, wherein: the processor is configured to: control the panel driving unit so that gate signals are sequentially output to a plurality of gate lines one gate line at a time, to process, in a first mode, image data in a first driving frequency, and control the panel driving unit so that the gate signals are output to the plurality of gate lines at least two gate lines at a time, to process, in a second mode, the image data in a second driving frequency higher than the first driving frequency; wherein, in the second mode, the respective gate lines output to the plurality of gate lines at least two gate lines at a time can have output timings that differ from each other.

A rollable display device includes a rollable structure including a plurality of unit structures, the rollable structure being configured to be rolled and unrolled based on the unit structures, and a display panel structure attached to the rollable structure, wherein respective widths of the unit structures increase in a first direction from a first side of the rollable structure to an opposite second side of the rollable structure.

The present disclosure provides a touch control display panel, a driving method thereof and a touch control display device. The touch control display panel includes a plurality of gate lines on a base substrate, a plurality of touch control lines above the plurality of gate lines and opposite to the plurality of gate lines, and a driving circuit, wherein the plurality of gate lines and the plurality of touch control lines extend along a same direction, and the driving circuit includes a timing controller, a control unit and a touch control driving unit. The timing controller is configured to output a gate driving signal to the control unit. The control unit is configured to generate touch control synchronization signal(s) according to the gate driving signal and output the touch control synchronization signal(s) to the touch control driving unit.

The present invention relates to a method for generating a reference signal to drive a display apparatus. A method according to the present invention may comprise generating a reference signal having a training pattern being repeated with a periodicity of two clock terms (CTs); and transmitting the reference signal to a phase locked loop (PLL). Each CT has a single embedded clock bit (CB) and a plurality of data bits, and the reference signal has a rising edge at a start point of a first CB corresponding to a first unit interval (UI) of a first CT, and a rising edge at an end point of a second CB corresponding to a first UI of a second CT. According to exemplary embodiments of the present disclosure, energy consumption and EMI effects can be remarkably reduced, and a complexity of PLL can be reduced.