In a first output mode, a signal in which a data pulse having a positive polarity voltage value appears in a predetermined cycle is output as a positive polarity gradation data signal, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with a phase different from the positive polarity gradation data signal is output as a negative polarity gradation data signal. In a second output mode, the above positive polarity gradation data signal is generated, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with the same phase as the positive polarity gradation data signal is output as the negative polarity gradation data signal. The first and second output modes are alternatively executed, and the output mode is switched within a predetermined period at intervals of the predetermined period.

To provide a semiconductor device, a liquid crystal display device, and an electronic device which have a wide viewing angle and in which the number of manufacturing steps, the number of masks, and manufacturing cost are reduced compared with a conventional one. The liquid crystal display device includes a first electrode formed over an entire surface of one side of a substrate; a first insulating film formed over the first electrode; a thin film transistor formed over the first insulating film; a second insulating film formed over the thin film transistor; a second electrode formed over the second insulating film and having a plurality of openings; and a liquid crystal over the second electrode. The liquid crystal is controlled by an electric field between the first electrode and the second electrode.

A comparator circuit according to the present embodiment: including a comparator element configured to output a matching signal indicating whether or not a value of a first input signal matches a value of a second input signal; a flip-flop circuit including a data input terminal to which a constant potential is supplied and a clock input terminal and configured to hold a value of the data input terminal based on a self-clock signal input to the clock input terminal; and a clock generation circuit configured to generate the self-clock signal based on the matching signal.

An interface circuit comprises a timing signal generating unit that generates a timing signal indicating a timing to switch between a data input period and a non-input period, a plurality of driver error detection circuits that detects an error in source drivers, a selector circuit that selects one of the driver error detection circuits in the non-input period and that outputs a driver error detection signal indicating an error detection result, an input error detection circuit that detects an input error of a data signal and outputs an input error detection signal indicating the result, an OR circuit that outputs an OR of the driver error detection signal and the input error detection signal, and a signal output unit connected to an output part of the OR circuit.

A gamma reference voltage generator includes a first resistor string, black voltage setters, a selector, and a second resistor string. The first resistor string receives a first reference voltage and a second reference voltage. The black voltage setters extract a plurality of black candidate voltages from the first resistor string. The selector selects one of the black candidate voltages as a black gamma voltage based on a selection signal. The second resistor string receives a first voltage corresponding to one of the black candidate voltages and a second voltage extracted from the first resistor string. In addition, the gamma reference voltage generator includes gamma voltage setters that extract a plurality of gamma voltages from the second resistor string.

A chip on film, a display panel, and a method of manufacturing the display panel are provided. The chip on film includes a flexible film and a driver chip. The flexible film includes at least a first group of lines and a second group of lines. M lines of the first group of lines are electrically connected to pins of the driver chip to form driver lines; and N lines of the secondgroup of lines are not electrically connected to any pin of the driver chip, serving as nominal lines. By arranging the nominal lines, a conventional bonding machine may be applied to bond the chip on film to the display substrate. Costs for modifying the bonding machine may be reduced, and application scenarios of the chip on film may be increased.

A display device capable of performing image processing is provided. A memory node is provided in each pixel included in the display device. An intended correction data is held in the memory node. The correction data is calculated by an external device and written into each pixel. The correction data is added to image data by capacitive coupling, and the resulting data is supplied to a display element. Thus, the display element can display a corrected image. The correction enables image upconversion, for example.

A display apparatus includes a display panel including a first surface including first pixels and a second surface including second pixels, the first surface contacting the second surface at a panel center thereof, a first source integrated circuit (IC) sequentially latching first image data, which is to be applied to the first surface, in a first direction facing the panel center at a panel edge of the first surface, and a second source IC sequentially latching second image data, which is to be applied to the second surface, in a second direction facing the panel center at a panel edge of the second surface, wherein the first direction is opposite to the second direction.

The present embodiment provides a technology for sensing a common mode voltage in the positive line and negative line of a transmission line for image data and determining whether noise occurs in the image data transmitted through the transmission line by comparing the common mode voltage with a set reference voltage.

A control method for charging time sharing in a display apparatus, which includes receiving image data including a plurality of pixel data signals corresponding to a plurality of display driving periods, each display driving period associated with pixel data signals of a respective row of the display apparatus, calculating a plurality of gray variations corresponding to the plurality of display driving periods according to the plurality of pixel data signals, adjusting the plurality of display driving periods to generate a plurality of adjusted display driving periods according to the plurality of gray variations, and generating a gate clock signal according to the plurality of adjusted display driving periods.