Disclosed is a source amplifier which includes a first circuit that outputs a first current to an output terminal of the source amplifier by amplifying an input voltage, and a second circuit that is connected with the first circuit and outputs a second current to the output terminal based on the input voltage. The second circuit includes a third circuit that adjusts a level of the second current in response to an enable signal.

A display driver includes first and second level shifters, respectively receiving a digital signal's most significant bit (MSB) and the digital signal's non-MSB. The first level shifter includes a first input terminal, a first output terminal via which a signal input to the first input terminal is output, a second input terminal, and a second output terminal via which a signal input to the second input terminal is output. The second level shifter includes a third input terminal, a third output terminal via which a signal input to the third input terminal is output, a fourth input terminal, and a fourth output terminal via which a signal input to the fourth input terminal is output. The first input terminal receives an inverted MSB, the second input terminal receives the MSB, the third input terminal receives the non-MSB, and the fourth input terminal receives the inverted non-MSB.

A display device is provided and includes scanning and signal lines; switch electrically coupled to scanning and signal lines; pixel electrode electrically coupled to switch and opposed to drive electrode; first and second display periods, and detection period between first and second display periods, wherein during first and second display periods, common voltage is applied to drive electrode, scanning signal is applied to scanning line and switch, pixel signal is applied to pixel electrode through signal line and switch, during detection period, AC drive signal or pulse drive signal is applied to drive electrode, and scanning signal is not applied to scanning line.

A display device including a display panel configured to display an image, a data driver configured to supply a data voltage to the display panel and having a precharge circuit configured to perform a precharging operation, and a timing controller configured to control the data driver, wherein the charge circuit generates a precharge voltage based on a precharge signal supplied in a horizontal blank period and is controlled to output or not output the precharge voltage based on a precharge selection signal.

A driving device of a display panel and a display device are provided. A source driver expands display data of a low-resolution image to be displayed in a first working mode, and cooperates with the source driver to receive and processes display data of a high-resolution display image in a second working mode, which makes the driving device of the display panel has good compatibility.

A display driver comprises a decoder, a first source amplifier and a logic circuitry. The decoder is configured to output a grayscale voltage corresponding to an image data. The first source amplifier is configured to output a first source output voltage corresponding to the grayscale voltage to a first external output terminal. The logic circuitry is configured to generate fault detection data for fault detection of a test object connected to the first external output terminal. The fault detection data is based on a comparison output signal generated based on a comparison between a reference voltage and a voltage on the first external output terminal. The comparison is performed by the first source amplifier.

An electronic device has a display screen and a driver chip disposed on a driver area of the display screen. A fan-out area of the display screen has interconnects configured to provide electrical accesses to display elements of the display area. The driver chip includes a first edge, a second edge, and a row of electronic pads proximate to the first edge. The electronic pads have a first subset of end pads at a first end of the first row, a second subset of end pads at a second opposite end of the first row, and a subset of intermediate pads located between the first subset and second subset of end pads. The first subset of end pads physically contact a first subset of interconnects from the first edge, and the subset of intermediate pads physically contact a second subset of interconnects from the one or more second edges.

A buffer circuit according to an aspect of the inventive concepts include an operational amplifier configured to amplify an input voltage to generate an output voltage; a slew-rate compensating circuit configured to generate a compensation current based on a difference between a voltage level of the input voltage and a voltage level of the output voltage, and configured to provide the compensation current to the operational amplifier through a boosting transistor; and an offset blocking circuit configured to turn off the boosting transistor when the difference between the voltage level of the input voltage and the voltage level of the output voltage is less than a reference voltage level by providing a blocking current to the slew-rate compensating circuit.

The present disclosure provides a pixel structure, a method of driving the same and a display device. The pixel structure includes gate lines, data lines, and a plurality of subpixels arranged in an array form. Subpixels in each row correspond to two gate lines. Each data line corresponds to the subpixels in two adjacent columns, and each data line is arranged between the two adjacent columns of subpixels. Among the subpixels in each row, three adjacent subpixels are in different colors and forms a complete pixel unit. Among the subpixels in each column, three adjacent subpixels are in different colors and forms the complete pixel unit. Among the subpixels in two adjacent columns, the subpixels in two adjacent rows form two complete pixel units each including three subpixels, and two of the three subpixels are shared by the two pixel unit.

An electronic device has a display screen and a driver chip disposed on a driver area of the display screen. A fan-out area of the display screen has interconnects configured to provide electrical accesses to display elements of the display area. The driver chip includes a first edge, a second edge, and a row of electronic pads proximate to the first edge. The electronic pads have a first subset of end pads at a first end of the first row, a second subset of end pads at a second opposite end of the first row, and a subset of intermediate pads located between the first subset and second subset of end pads. The first subset of end pads physically contact a first subset of interconnects from the first edge, and the subset of intermediate pads physically contact a second subset of interconnects from the one or more second edges.