G11C11/0605

Greater than Binary State Digital Logic for Superconductive Circuits

In some embodiments, a multistate memory cell includes; a storage loop comprising one or more superconducting devices and one or more inductive devices, the storage loop configured to maintain a quantized magnetic field representing a stored state of the multistate memory cell, the stored state from among a set of three or more distinct digital states; and at least three address lines each inductively coupled to the storage loop, wherein, in response to currents applied to the at least three address lines, the inductive couplings of the at least three address lines combine to force the quantized magnetic field to represent a particular one of the three or more distinct digital states.