A magnetic recording array includes a plurality of spin elements arranged in a matrix, each spin element including a wiring and a stacked body that includes a first ferromagnetic layer stacked on the wiring, a plurality of write wirings connected to first ends of the respective wirings in the plurality of spin elements, a plurality of read wirings connected to the respective stacked bodies in the plurality of spin elements, and a plurality of common wirings connected to second ends of the wirings in the respective spin elements belonging to the same row, wherein the common wiring has an electrical resistance lower than the electrical resistance of the write wiring or the read wiring.

A semiconductor storage device and its writing method are provided. A memory cell array is formed on a substrate, and the memory cell array has an NOR array with an NOR flash memory structure and a resistive random access array with a resistive random access memory (RRAM) structure. A read/write control unit charges a selected global bit line when a set write operation is performed on a selected memory cell of the resistive random access array, and a set write voltage is applied to the selected memory cell by applying a voltage charging the selected global bit line.

A storage circuit includes a memory cell array of memory cells each including a variable resistance type element, a resistance-voltage conversion circuit RT.sub.j to convert a resistance value of a memory cell MC.sub.ij to be read to a data voltage, a reference circuit and RT.sub.R to generate a reference voltage, a sense amplifier to determine read data by receiving the data voltage and the reference voltage via first and second input terminals, respectively, and comparing both voltages with each other, and an analog buffer circuit arranged between the resistance-voltage conversion circuit RT.sub.j and a first input terminal of the sense amplifier or between the reference circuit and RT.sub.R and a second input terminal of the sense amplifier. Current driving capability of the analog buffer circuit is large.

A novel storage device is provided. The storage device includes a first wiring, a second wiring, and a first memory cell. The first memory cell includes a first transistor and a first magnetic tunnel junction device. One of a source or a drain of the first transistor is electrically connected to a first wiring. The other of the source or the drain of the first transistor is electrically connected to one terminal of the first magnetic tunnel junction device. Another terminal of the first magnetic tunnel junction device is electrically connected to the second wiring. The first transistor includes an oxide semiconductor in its channel formation region.

A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element, and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.

A semiconductor storage device includes a memory cell including a switching element and a variable resistance element, and a circuit for switching the memory cell ON, performing a first read operation on the memory cell, generating a first voltage based on the first read operation, switching the memory cell ON after first data is written to the memory cell, performing a second read operation while the memory cell is maintained to be ON when the first data is stored in the memory cell during the first read operation, performing the second read operation after the memory cell transitions from ON to OFF at least once when second data is stored in the memory cell during the first read operation, generating a second voltage based on the second read operation, and determining the data stored in the memory cell during the first read operation based on the first and second voltages.

In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines, each of the word lines coupled to a corresponding row of the memory cells; a plurality of bit lines, each of the bit lines coupled to a corresponding column of the memory cells; and a plurality of second word lines, each of the second word lines coupled to a corresponding column of the memory cells.

A storage circuit (11) includes memory cells (MCij), each of which includes an MTJ element, and reference cells (RCi), each of which includes a series circuit of an MTJ element set to a low-resistance state and a linear resistor (FR). A RW circuit (23j) that includes a sense amplifier is provided in each column of a memory cell array (21), and compares a data voltage on a corresponding bit line (BLj) with a reference voltage. The sense amplifier includes a pair of PMOS transistors to which the data voltage and the reference voltage are applied, a CMOS sense latch that is connected to a current path of the PMOS transistors.

A SOT-MRAM cell, comprising at least one magnetic tunnel junction (MTJ) comprising a tunnel barrier layer between a pinned ferromagnetic layer and a free ferromagnetic layer; a SOT line, extending substantially parallel to the plane of the layers and contacting a first end of said at least one MTJ; at least a first source line connected to one end of the SOT line; at least a first bit line and a second bit line, wherein the SOT-MRAM cell comprises one MTJ, each bit line being connected to the other end of the MTJ; or wherein the SOT-MRAM cell comprises two MTJs, each MTJ being connected to one of the first bit line and second bit line.

An electronic device comprising a semiconductor memory is provided. The semiconductor memory includes a substrate including a cell region and a peripheral circuit region, the cell region including a first cell region and a second cell region, the first cell region being disposed closer to the peripheral circuit region than the second cell region; second lines disposed over the first lines and extending in a second direction crossing the first direction; memory cells positioned at intersections between the first lines and the second lines in the cell region; a first insulating layer positioned between the first lines, between the second line, or both, in the first cell region; and a second insulating layer positioned between the first lines and between the second lines in the second cell region. A dielectric constant of the first insulating layer is smaller than that of the second insulating layer.