An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.

An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.

A read-port of a Static Random Access Memory (SRAM) cell includes a read-port pass-gate (R_PG) transistor and a read-port pull-down (R_PD) transistor. A write-port of the SRAM cell port includes at least a write-port pass-gate (W_PG) transistor, a write-port pull-down (W_PD) transistor, and a write-port pull-up (W_PU) transistor. The R_PG transistor, the R_PD transistor, the W_PG transistor, the W_PD transistor, and the W_PU transistor are gate-all-around (GAA) transistors. The R_PG transistor has a first channel width. The R_PD transistor has a second channel width. The W_PG transistor has a third channel width. The W_PD transistor has a fourth channel width. The W_PU transistor has a fifth channel width. The first channel width and the fourth channel width are each smaller than the second channel width. The third channel width is greater than the fifth channel width.

A read-port of a Static Random Access Memory (SRAM) cell includes a read-port pass-gate (R_PG) transistor and a read-port pull-down (R_PD) transistor. A write-port of the SRAM cell port includes at least a write-port pass-gate (W_PG) transistor, a write-port pull-down (W_PD) transistor, and a write-port pull-up (W_PU) transistor. The R_PG transistor, the R_PD transistor, the W_PG transistor, the W_PD transistor, and the W_PU transistor are gate-all-around (GAA) transistors. The R_PG transistor has a first channel width. The R_PD transistor has a second channel width. The W_PG transistor has a third channel width. The W_PD transistor has a fourth channel width. The W_PU transistor has a fifth channel width. The first channel width and the fourth channel width are each smaller than the second channel width. The third channel width is greater than the fifth channel width.

A method of memory reset includes precharging bit lines of a memory array, asserting a signal at a reset node to remove the precharge voltage, and selecting write drivers associated with the bit lines associated with columns of the memory array that contain memory cells to be reset, with the assertion of the signal at the reset node also resulting in application of desired logic states to inputs of the selected write drivers to cause those selected write drivers to change a logic state of the bit lines associated with those write drivers. The method continues with asserting each word line associated with a row of the memory that contains memory cells to be reset to write desired logic states to all of the memory cells of the columns and rows of the memory to be reset during a single clock cycle, and then deasserting those word lines.

A method of memory reset includes precharging bit lines of a memory array, asserting a signal at a reset node to remove the precharge voltage, and selecting write drivers associated with the bit lines associated with columns of the memory array that contain memory cells to be reset, with the assertion of the signal at the reset node also resulting in application of desired logic states to inputs of the selected write drivers to cause those selected write drivers to change a logic state of the bit lines associated with those write drivers. The method continues with asserting each word line associated with a row of the memory that contains memory cells to be reset to write desired logic states to all of the memory cells of the columns and rows of the memory to be reset during a single clock cycle, and then deasserting those word lines.

A memory device includes a first SRAM cell, a second SRAM cell, a first inter transistor and a second inter transistor. The first SRAM cell includes two first pull-up transistors, two first pull-down transistors, and two first pass-gate transistors. The second SRAM cell includes two second pull-up transistors, two second pull-down transistors, and two second pass-gate transistors. The first inter transistor and the second inter transistor are electrically connected to the first SRAM cell and the second SRAM cell.

A memory device includes a first SRAM cell, a second SRAM cell, a first inter transistor and a second inter transistor. The first SRAM cell includes two first pull-up transistors, two first pull-down transistors, and two first pass-gate transistors. The second SRAM cell includes two second pull-up transistors, two second pull-down transistors, and two second pass-gate transistors. The first inter transistor and the second inter transistor are electrically connected to the first SRAM cell and the second SRAM cell.

The present disclosure describes embodiments of a memory system with a memory cell power supply. The memory system can include a circuit with a first voltage supply, a second voltage supply, pull-up devices, pull-down devices, and pass devices. The first voltage supply is configured to provide a first voltage. The first voltage supply is configured to apply the first voltage to gate terminals of the pass devices. The second voltage supply is electrically coupled to S/D terminals of the pull-up devices and is configured to transition from the first voltage to the second voltage for a read operation.

The present disclosure describes embodiments of a memory system with a memory cell power supply. The memory system can include a circuit with a first voltage supply, a second voltage supply, pull-up devices, pull-down devices, and pass devices. The first voltage supply is configured to provide a first voltage. The first voltage supply is configured to apply the first voltage to gate terminals of the pass devices. The second voltage supply is electrically coupled to S/D terminals of the pull-up devices and is configured to transition from the first voltage to the second voltage for a read operation.