A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

A semiconductor chip may include a memory, a power supply line, a noise generator and a switch. The power supply line may include first and second power supply line portions. The power supply line may be configured to provide a power supply signal through each of the first power supply line portion and the second power supply line portion. The noise generator may be connected to the second power supply line portion. The noise generator may be configured to receive the power supply signal from the second power supply line portion, and output a noisy power supply signal based on the power supply signal. The switch may be coupled to the memory, the first power supply line portion, and the noise generator. The switch may be configured to selectively electrically connect the memory to one of the first power supply line portion and the noise generator.

A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.

A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.

A memory sub-system configured to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory sub-system. For example, after receiving a plurality of streams of write commands from a host system, the memory sub-system identifies a plurality of media units in the memory sub-system for concurrent execution of a plurality of write commands respectively. In response to the plurality of commands being identified for concurrent execution in the plurality of media units respectively, the memory sub-system initiates communication of the data of the write commands from the host system to a local buffer memory of the memory sub-system. The memory sub-system has capacity to buffer write commands in a queue, for possible out of order execution, but limited capacity for buffering only the data of a portion of the write commands that are about to be executed.

Aspects of the invention include a first pull-down device and a second pull-down device, wherein a first drain terminal is connected to a second source terminal, and wherein a first gate terminal is connected to a true read local bitline, wherein a second drain terminal is connected to a compliment read local bit line, and wherein a second gate terminal is connected to a true write global bitline, a third pull-down device and a fourth pull-down device, wherein a third source terminal is connected to the voltage supply, wherein a third drain terminal is connected to a fourth source terminal, and wherein a third gate terminal is connected to the compliment read local bitline, and wherein a fourth drain terminal is connected to the true read local bitline, and wherein a fourth gate terminal is connected to a compliment write global bit line.

Aspects of the invention include a first pull-down device and a second pull-down device, wherein a first drain terminal is connected to a second source terminal, and wherein a first gate terminal is connected to a true read local bitline, wherein a second drain terminal is connected to a compliment read local bit line, and wherein a second gate terminal is connected to a true write global bitline, a third pull-down device and a fourth pull-down device, wherein a third source terminal is connected to the voltage supply, wherein a third drain terminal is connected to a fourth source terminal, and wherein a third gate terminal is connected to the compliment read local bitline, and wherein a fourth drain terminal is connected to the true read local bitline, and wherein a fourth gate terminal is connected to a compliment write global bit line.