Certain aspects of the present disclosure generally relate to electrically erasable programmable read-only memory (EEPROM) device comprising at least one EEPROM cell structure. The EEPROM device generally includes a first active region, a second active region, a channel region disposed between the first active region and the second active region, a floating gate structure disposed above the channel region and separated from the channel region by a first dielectric layer, a control gate structure disposed above the floating gate structure and separated from the floating gate structure by a second dielectric layer, and a bottom gate structure disposed below the channel region.

Techniques described herein generally relate to the fabrication of a P-type metal-oxide-semiconductor (PMOS) flash memory cell in a semiconductor substrate. The PMOS flash memory cell may include a P-substrate layer formed above the semiconductor substrate, a N-well formed in the P-substrate layer, a floating-gate formed above the N-well. Further, the PMOS memory cell may include a control-gate formed above the floating-gate, a select-gate formed above the N-well and extending over at least a portion over the floating-gate, a P-source formed in the N-well, and a P-Drain. The P-source is formed adjacent to the floating-gate, and the P-drain is formed adjacent to the select-gate.

A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation.

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

A selective non-volatile memory programming method for a selected memory cell in a memory array is described so as to reduce or avoid program disturbance on an unselected memory cell. This selective programming method comprises: applying a programming pulse to a selected memory cell to be programmed and an unselected memory cell, wherein the programming pulse allows a change of the unselected memory cell within a range specified; boosting a region of the unselected memory cell; and setting a threshold time of the programming pulse, wherein the threshold time is defined when an absolute magnitude of a voltage difference between a floating gate of the unselected memory cell and the boosted region of the unselected memory cell reaches a threshold value defined.

A memory device includes word lines stacked on an upper surface of a substrate, channel structures penetrating through the word lines, and each including channel regions connected to one another in a first direction perpendicular to the upper surface of the substrate, and word-line cuts extending in the first direction and dividing the word lines to blocks. The word lines and the channel structures provide memory cell strings, and each of the memory cell strings include memory cells arranged in the first direction. The memory cells included in at least one of the memory cell strings include a first memory cell and a second memory cell disposed at different positions in the first direction, and the number of bits of data stored in the first memory cell is less than the number of bits of data stored in the second memory cell.

A serialized neural network computing unit is disclosed. This computing unit comprises: a bit line; a memory array having a plurality of memory blocks, each memory block have one or more than one memory cells, each cell connected to the bit line; a control circuit configured to: apply a serialized input to the memory cells in a sequence such that outputs of the memory cells are produced in a sequence in response to the serialized input, wherein each of the outputs corresponds to a multiplication of the input and a weight value stored in the memory cell; and set a group of reference current levels, each having a specific current amount, for the control circuit to control the memory cells in generating respective output currents corresponding to the set of reference current levels.

A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation.

A memory device includes word lines stacked on an upper surface of a substrate, channel structures penetrating through the word lines, and each including channel regions connected to one another in a first direction perpendicular to the upper surface of the substrate, and word-line cuts extending in the first direction and dividing the word lines to blocks. The word lines and the channel structures provide memory cell strings, and each of the memory cell strings include memory cells arranged in the first direction. The memory cells included in at least one of the memory cell strings include a first memory cell and a second memory cell disposed at different positions in the first direction, and the number of bits of data stored in the first memory cell is less than the number of bits of data stored in the second memory cell.

An analog multiplier accumulator array comprises analog multipliers organized in a matrix of rows and columns, each of the multiplier comprising one or more than one analog input signal line coupled to the analog multipliers in a row of the array; an analog level sensing circuit; a set of bit lines, each bit line electrically connected to the analog multiplier in each column of the row; and an analog accumulator configured to connect the set of the bit lines to an analog level sensing circuit for generating digital output signals, wherein an access transistor connected to the analog input line and a variable resistor form the analog multiplier.