A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

An ESD circuit is connected with a pad. The ESD circuit includes a voltage divider, a RC circuit and a path control circuit. The voltage divider is connected between the pad and a first node and provides plural divided voltages. The RC circuit is connected between the pad and the first node. The RC circuit receives the plural divided voltages and provides a control circuit. The path control circuit is connected with the pad and the first node. The path control circuit receives the plural divided voltages and the control voltage. When the pad receives a first ESD zap, the RC circuit controls the path control circuit to turn on a first ESD current path. Consequently, an ESD current flows from the pad to the first node through the first ESD current path.

Semiconductor device, memory arrays, and methods of forming a memory cell include or utilize one or more memory cells. The memory cell(s) include a first nanosheet transistor connected to a first terminal, a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal, and an access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.

An erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. A select gate and a first source/drain terminal of the first select transistor receive a select gate voltage and a first source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the first floating gate transistor are connected with a second source/drain terminal of the first select transistor and a first bit line voltage, respectively. The second select transistor also includes the select gate. A first source/drain terminal of the second select transistor receive a second source line voltage. A first source/drain terminal and a second source/drain terminal of the second floating gate transistor are connected with the second source/drain terminal of the second select transistor and a second bit line voltage, respectively.

An erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. A select gate and a first source/drain terminal of the first select transistor receive a first select gate voltage and a first source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the first floating gate transistor are connected with a second source/drain terminal of the first select transistor and a first bit line voltage, respectively. A select gate and a first source/drain terminal of the second select transistor receive a second select gate voltage and a second source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the second floating gate transistor are connected with the second source/drain terminal of the second select transistor and a second bit line voltage, respectively.

A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region.

The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.

The application provides a memory device and an operation method thereof. The memory device includes: a memory array, for processing model computation having a plurality of input values and a plurality of interact coefficients; and at least one calculation unit. In receiving the input values, a first part and a second part of the memory cells generate a first part and a second part of the common source currents, respectively. The first part of the memory cells is electrically isolated from the second part of the memory cells based on a diagonal of the memory array. The at least one calculation unit calculates a first part and a second part of a local field energy of the model computation based on the first part and the second part of the common source currents.

Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.

Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.

To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.