A memory device includes memory cells in rows, word lines respectively coupled to the rows, and a control circuitry coupled to the memory cells via the word lines. The control circuitry is configured to apply a first program voltage to a first word line of the word lines. The first word line is coupled to a first row of the memory cells. The control circuitry is also configured to, after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the word lines. The second word line is coupled to a second row of the memory cells. The control circuitry is also configured to, after applying the second program voltage to the second word line, apply a first pre-charge voltage to the first word line and a second pre-charge voltage to the second word line. The second pre-charge voltage is greater than the first pre-charge voltage.

A memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of strings. A method of programming the memory device includes programming a first row of the memory cells. The method also includes, after programing the first row of the memory cells, programming a second row of the memory cells. The second row is adjacent to the first row in a first string direction. The method further includes, after programming the second row of the memory cells, programming a third row of the memory cells. The third row is two rows apart from the second row in a second string direction opposite to the first string direction.

A memory device including a plurality of memory cells, configured to perform a read operation of reading data from memory cells connected to a selected word line, and configured to apply a plurality of read voltages to the selected word line, apply a first pass voltage to unselected word lines while first read voltages for determining a program state of memory cells having a threshold voltage higher than a reference voltage among the plurality of read voltages are applied to the selected word line, and apply a second pass voltage higher than the first pass voltage to the unselected word line while second read voltages for determining a program state of memory cells having a threshold voltage lower than the reference voltage among the plurality of read voltages are applied to the selected word line.

Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells coupled between a common source line and a bit line, a peripheral circuit configured to perform a plurality of program loops, each including a program voltage application operation of applying a program voltage to a selected memory cell and a verify operation of verifying a program state of the selected memory cell, and a control logic configured to control, at the program voltage application operation, the peripheral circuit to apply a precharge voltage to the common source line and change at least one of a magnitude of the precharge voltage and a time during which the precharge voltage is applied, depending on a magnitude of the program voltage.

An example method includes maintaining a first data structure comprising logical address to physical address mappings for managed units corresponding to a memory, and maintaining a second data structure whose entries correspond to respective physical managed unit addresses. Each entry of the second data structure comprises an activity counter field corresponding to the respective physical managed unit address and a number of additional fields indicating whether the respective physical managed unit address is in one or more of a number of additional data structures. The one or more additional data structures are accessed in association with performing at least one of a wear leveling operation on the respective physical managed unit address, and a neighbor disturb mitigation operation on physical managed unit addresses corresponding to neighbors of the respective physical managed unit address.

A semiconductor memory device includes a cell string and a peripheral circuit. The cell string includes at least one drain select transistor that is connected to a bit line, at least one source select transistor that is connected to a common source line, and a plurality of memory cells that are connected between the drain select transistor and the source select transistor. The peripheral circuit performs a read operation on a selected memory cell among the plurality of memory cells. The peripheral circuit is configured to read data that is stored in the selected memory cell by applying a read voltage to a selected word line among word lines that are connected to the plurality of memory cells and by applying a pass voltage to unselected word lines, and configured to transmit a boosting prevention voltage to a channel region in the cell string while applying an equalizing voltage to the word lines.

A method for performing a read of a flash memory includes storing configuration files for a plurality of RRD-compensating RNNs. A current number of PE cycles for a flash memory are identified and TVSO values are identified corresponding to the current number of PE cycles. A current retention time and a current number of read disturbs for the flash memory are identified. The configuration file of the RRD-compensating RNN corresponding to the current number of PE cycles, the current retention time and current number of read disturbs is selected and is loaded into a neural network engine to form an RNN core in the neural network engine. A neural network operation of the RNN core is performed to predict RRD-compensated TVSO values. The input to the neural network operation includes the identified TVSO values. A read of the flash memory is performed using the predicted RRD-compensated TVSO values.

According to an exemplary embodiment of the inventive concept, there is provided a nonvolatile memory device comprising: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array, in the memory cell region, comprising a plurality of memory cells, a plurality of word lines and a bit line connected to the memory cells, wherein each memory cell is connected to one of the word lines, a voltage generator, in the peripheral circuit region, supplying a plurality of supply voltages to the memory cell array, a control logic circuit, in the peripheral circuit region, programming a selected one of the memory cells connected to a selected one of the word lines into a first program state by controlling the voltage generator, and a verify circuit, in the peripheral circuit region, controlling a verify operation on the memory cell array by controlling the voltage generator, wherein the verify circuit controls a word line voltage applied to at least one unselected word line not to be programmed among the plurality of word lines in the verify operation and a bit line voltage applied to the bit line connected differently from a voltage level of a voltage applied in a read operation of the nonvolatile memory device.

A memory device includes: one or more planes each including a plurality of memory blocks; and a control circuit for selectively performing a dummy read operation before a valid read operation on the first memory block, according to whether a read command on the first memory block is firstly received from a host after a program operation is performed on a plane including the first memory block.

A selective non-volatile memory programming method for a selected memory cell in a memory array is described so as to reduce or avoid program disturbance on an unselected memory cell. This selective programming method comprises: applying a programming pulse to a selected memory cell to be programmed and an unselected memory cell, wherein the programming pulse allows a change of the unselected memory cell within a range specified; boosting a region of the unselected memory cell; and setting a threshold time of the programming pulse, wherein the threshold time is defined when an absolute magnitude of a voltage difference between a floating gate of the unselected memory cell and the boosted region of the unselected memory cell reaches a threshold value defined.