A memory device and method for a non-volatile memory cell having a gate that includes programming the memory cell to an initial program state corresponding to a target read current and a threshold voltage, including applying a program voltage having a first value to the gate, storing the first value in a memory, reading the memory cell in a first read operation using a read voltage applied to the gate that is less than the target threshold voltage to generate a first read current, and subjecting the memory cell to additional programming in response to determining that the first read current is greater than the target read current. The additional programming includes retrieving the first value from the memory, determining a second value greater than the first value, and programming the selected non-volatile memory cell that includes applying a program voltage having the second value to the gate.

Memories might include a plurality of strings of memory cells, a plurality of access lines each connected to the strings of memory cells, and a controller configured to cause the memory to determine a particular voltage level applied to each of the access lines that is deemed to activate each memory cell of a first subset of the strings of series-connected memory cells programmed to store respective data states that are each lower than or equal to a first data state of a plurality of data states, apply the particular voltage level to a particular access line of the plurality of access lines, and for each memory cell connected to the particular access line that is contained in a second subset of the strings of series-connected memory cells, determine whether that memory cell is deemed to be activated while applying the particular voltage level to the particular access line.

A semiconductor device includes a transmission and reception circuit and a control circuit. The transmission and reception circuit transmits and receives a signal to and from a semiconductor memory device. The control circuit acquires threshold voltage distribution information of a memory element connected to a word line for read disturb detection to which a second voltage higher than a first voltage applied to an adjacent word line adjacent to a read target word line during a read operation is applied and determines an influence of read disturb based on the threshold voltage distribution information.

Control logic in a memory device initiates a read operation on a memory array of the memory device and performs a calibration operation to detect a change in string resistance in the memory array. The control logic determines whether the change in string resistance is attributable to charge loss in the memory array, and responsive to determining that the change in string resistance is attributable to charge loss in the memory array, preforms the read operation using calibrated read voltage levels to read data from the memory array.

One or more write operations are performed on a memory component. First data stored at the memory component is read. A determination is made as to whether an error rate associated with the first data stored at the memory component exceeds an error rate threshold. If the error rate exceeds the error rate threshold, a threshold value is adjusted. A determination is made as to whether a number of the plurality of write operations performed on the memory component since performance of a refresh operation on the memory component exceeds the threshold value. In response to determining that the number of write operations performed on the memory component exceeds the threshold value, a memory cell of the memory component is identified based on the plurality of write operations. Second data stored at memory cells of the memory component that are proximate to the identified memory cell is refreshed.

A method for detecting and isolating defective memory plane(s) of a non-volatile memory structure during a program verify operation, comprising: initiating, for each plane, a word line verify voltage level scan with a bit scan pass fail criterion and at a starting voltage located within an intended program threshold voltage distribution curve, incrementally decreasing the word line verify voltage by a predetermined offset until a specific condition of the scan is obtained, and storing the voltage at which the specific condition of the scan is obtained, wherein the stored voltage represents a voltage of an upper tail portion of an actual programmed threshold voltage distribution curve of the plane. The stored voltages of all of the memory planes of the structure are compared to determine which plane corresponds to the lowest stored voltage. A “fail” status is applied to the plane corresponding to the lowest stored voltage.

A variety of applications can include memory devices designed to provide stabilization of selector devices in a memory array of the memory device. A selector stabilizer pulse can be applied to a selector device of a string of the memory array and to a memory cell of multiple memory cells of the string with the memory cell being adjacent to the selector device in the string. The selector stabilizer pulse can be applied directly following an erase operation to the string to stabilize the threshold voltage of the selector device. The selector stabilizer pulse can be applied as part of the erase algorithm of the memory device. Additional devices, systems, and methods are discussed.

An apparatus includes circuitry configured to generate multiple results, each result using a different read voltage, in response to one or each received data access command. The multiple read results may be used to dynamically calibrate a read voltage assigned to generate a read result in response to a read command.

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines including at least one edge word line and a plurality of other data word lines. The memory cells are arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means coupled to the plurality of word lines and the strings. The control means is configured to identify the at least one edge word line. The control means is also configured to periodically apply a program voltage to the at least one edge word line to reprogram the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line.

A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.