A system, method and apparatus of memory failure prediction through image analyses using an artificial neural network. A sequence of images indicative of progress of memory failures in a region of an integrated circuit die can be generated according to a physical layout of memory cells in the region. The artificial neural network can be trained to recognize graphical features in early images in the sequence and to predict, based on the recognized graphical features, memory failures shown in subsequent images in the sequence. A computing apparatus can use the artificial neural network to analyze an input image shown current memory failures in the region and to identify one or more memory cells in the region that are likely to have subsequent memory failures.

An apparatus can include an array of memory cells and control circuitry coupled to the array of memory cells. The control circuitry can be configured to store a number of trim settings and receive signaling indicative of a use of the array of memory cells. The control circuitry can be configured to determine an adjustment to the number of trim settings based at least in part on the signaling.

A testing device comprises test interface circuitry, probe circuitry, and initiate state machine circuitry. The test interface circuitry is configured to receive NAND signaling when operatively coupled to a M-NAND memory device under test and to operate the M-NAND memory device under test to receive memory access requests and to provide status or data at the same rate it receives memory access requests. The probe circuitry is configured to detect memory operations of the memory device under test. The finite state machine circuitry is operatively coupled to the probe circuitry and is configured to advance through multiple circuit states according to the detected memory operations; and log memory events of the memory device under test according to the circuit states.

A testing device comprises test interface circuitry, probe circuitry, and initiate state machine circuitry. The test interface circuitry is configured to receive NAND signaling when operatively coupled to a M-NAND memory device under test and to operate the M-NAND memory device under test to receive memory access requests and to provide status or data at the same rate it receives memory access requests. The probe circuitry is configured to detect memory operations of the memory device under test. The finite state machine circuitry is operatively coupled to the probe circuitry and is configured to advance through multiple circuit states according to the detected memory operations; and log memory events of the memory device under test according to the circuit states.

In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

An apparatus can include an array of memory cells and control circuitry coupled to the array of memory cells. The control circuitry can be configured to store a number of trim settings and receive signaling indicative of a use of the array of memory cells. The control circuitry can be configured to determine an adjustment to the number of trim settings based at least in part on the signaling.

A memory circuit configured to perform multiply-accumulate (MAC) operations for performance of an artificial neural network includes a series of synapse cells arranged in a cross-bar array. Each cell includes a memory transistor connected in series with a memristor. The memory circuit also includes input lines connected to the source terminal of the memory transistor in each cell, output lines connected to an output terminal of the memristor in each cell, and programming lines coupled to a gate terminal of the memory transistor in each cell. The memristor of each cell is configured to store a conductance value representative of a synaptic weight of a synapse connected to a neuron in the artificial neural network, and the memory transistor of each cell is configured to store a threshold voltage representative of a synaptic importance value of the synapse connected to the neuron in the artificial neural network.

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of memory states. A control circuit is coupled to the plurality of word lines and strings and is configured to erase the memory cells using a stripe erase operation in response to determining a cycle count is less than a predetermined cycle count maximum threshold. The control circuit is also configured to perform a dummy cycle operation in response to determining the cycle count is not less than the predetermined cycle count maximum threshold.

A tool for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis. The tool stores a configurable test signature in a random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory. The tool determines an error based, at least in part, on a compare operation for a given test pattern, wherein the compare operation determines whether the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature. The tool stores the error in a corresponding additional signature register.