Systems and methods are provided for reading data from non-volatile storage devices and decoding the read data. A method may include obtaining a unique identifier for a storage location to be read, retrieving from a memory an adjustment to read reference voltage (Vref) associated with the unique identifier, performing a read operation on the storage location using a read reference voltage adjusted by the adjustment to Vref, decoding data read from the storage location in a decoding process and updating the adjustment to V.sub.ref with decoding information generated during the decoding process.

Various implementations described herein relate to systems and methods for detecting address corruption when using a memory device to store and retrieve data, including but not limited to, reading combined information from a memory device, determining encoded data by de-combining address information from the combined information, and detecting address corruption by decoding the encoded data.

The present disclosure includes methods and apparatuses comprising a memory component having an independent structure and including an array of memory cells with associated decoding and sensing circuitry of a read interface, a host device coupled to the memory component through a communication channel, a JTAG interface in the array of memory cells, and an additional register in the JTAG interface. The additional register is configured to store a page address associated with the array of memory cells, the memory component is configured to load the page address at the power-on of the apparatus, and the host device is configured to perform a read sequence at the page address.

The present disclosure includes apparatuses, methods, and systems for programming codewords for error correction operations to memory. An embodiment includes a memory having a plurality of groups of memory cells, wherein each respective one of the plurality of groups includes a plurality of sub-groups of memory cells, and circuitry configured to program a portion of a codeword for an error correction operation to one of the plurality of groups of memory cells by determining an address in that group of memory cells by performing an XOR operation on an address of one of the plurality of sub-groups of that group of memory cells, and programming the portion of the codeword to the determined address.

A data processing system includes a memory configured to receive memory access requests. Each memory access request having a corresponding access address and having a corresponding parity bit for an address value of the corresponding access address. The corresponding access address is received over a plurality of address lines and the parity bit is received over a parity line. The memory includes a memory array having a plurality of memory cells arranged in rows, each row having a corresponding word line of a plurality of word lines, and a row decoder coupled to the plurality of address lines, the parity line, and the plurality of word lines. The row decoder is configured to selectively activate a selected word line of the plurality of word lines based on the corresponding access address and the corresponding parity bit of a received memory access request. The concept can also be used with parity bits on columns of the memory cells and a column decoder that selects bit lines associated with column address lines.

Embodiments disclosed herein include a semiconductor device. The semiconductor device may include a magnetoresistive random access memory (MRAM) array. The MRAM array may include defective MRAM cells, redundancy MRAM cells, and operational MRAM cells. The semiconductor device may also include an address input electrically connected to the MRAM array and a selector circuit wired to the address input and an output of the MRAM array. The selector circuit may be configured to read the defective MRAM cells to identify the MRAM array.

A memory device and its addressing method are disclosed. The memory device includes: an input module for receiving an input signal including an access address, a command, and a decoding selection instruction; a memory array including memory blocks, each having memory units arranged in an array; and a control module including memory block local control units, which respectively connected to one of the memory blocks in one-to-one correspondence. The memory block local control unit includes: at least one decoding unit, which performs redundant decoding or normal decoding to the input signal. The input of the decoding unit is coupled to the input module and the output is coupled to one of the memory units. The device further includes a selection module; the input of the selection module is coupled to the input module, and the output is coupled to the decoding unit. The addressing efficiency of the memory device is improved.

A read/write method and a memory are provided. The read/write method includes: issuing a read command to a memory, wherein the read command points to an address; reading to-be-read data from a storage unit corresponding to the address to which the read command points; and in response to an error occurring in the to-be-read data, marking the address to which the read command points as disabled. When executing a read/write operation on the memory, the address of the storage unit is marked to distinguish an enabled storage unit from a failed storage unit in real time. A data error or a data loss can be avoided, thereby greatly improving the reliability and the service life of the memory.

A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.

A memory controller and a storage device including the same are provided. The memory controller performs decoding by selecting a decoder of a level enough to correct bit errors in a codeword from among a plurality of error correction code (ECC) decoders based on a bit error history of a non-volatile memory device.