Techniques for providing temperature trim codes to multiple reference circuits of an integrated circuit are provided. In an example, a string of primary latch circuits can provide a set of pre-defined temperature trim codes to a multiplexer in response to a token of a series of tokens. The multiplexer can provide two trim of the trim codes to an interpolator based on a temperature reading of the integrated circuit. The interpolator can provide an interpolated trim code and the trim code can be distributed to a reference circuit based on the token.

A memory system is provided. The memory system includes a compare circuit and a control circuit. The compare circuit determines, in response to a number of detected error bits in a read data from a first memory array, whether a fail word address associated with the detected error bits is in an error table. The control circuit increments a counter value corresponding to the fail word address when the fail word address is in the error table, and further compares the counter value with a threshold value to replace memory locations, corresponding to the fail word address, in the first memory array with backup memory locations in a second memory array.

A memory system is provided. The memory system includes a compare circuit and a control circuit. The compare circuit determines, in response to a number of detected error bits in a read data from a first memory array, whether a fail word address associated with the detected error bits is in an error table. The control circuit increments a counter value corresponding to the fail word address when the fail word address is in the error table, and further compares the counter value with a threshold value to replace memory locations, corresponding to the fail word address, in the first memory array with backup memory locations in a second memory array.

A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.

Disclosed herein is an apparatus that includes a first circuit configured to measure a first time period from a first active edge of one of plurality of internal signals to a second active edge of one of the plurality of internal signals, and a second circuit configured to compare the first time period with a second time period to generate an alert signal.

The present technology relates to an electronic device. According to the present technology, a memory device having reduced latency includes a plurality of memory cells, an optimum read voltage information storage configured to store optimum read voltage information determined according to a cell count value, which is the number of memory cells read as a first memory cell based on data read from the plurality of memory cells among the plurality of memory cells, and a read voltage controller configured to calculate a cell count value corresponding to a default read voltage based on the data read from the plurality of memory cells using the default read voltage, in response to an optimum read voltage setting command input from a memory controller, and generate a first optimum read voltage based on the cell count value corresponding to the default read voltage and the optimum read voltage information.

Calibration of soft bit reference levels in a non-volatile memory system is disclosed. A set of memory cells are sensed at a hard bit reference level and test soft bit reference levels. The test soft bit reference levels are grouped around the hard bit reference level. A metric is determined for the test soft bit reference levels. Bins are defined based on the hard bit reference level and the set of test soft bit reference levels. A metric may be determined for each of the bins. The new soft bit reference levels are determined based on the metric. In one aspect, the metric is how many memory cells have a value for a physical parameter within each bin. The soft bit reference levels may be established based on a target percentage for the bins. In one aspect, the metric is how many unsatisfied counters are within each bin.

Calibration of soft bit reference levels in a non-volatile memory system is disclosed. A set of memory cells are sensed at a hard bit reference level and test soft bit reference levels. The test soft bit reference levels are grouped around the hard bit reference level. A metric is determined for the test soft bit reference levels. Bins are defined based on the hard bit reference level and the set of test soft bit reference levels. A metric may be determined for each of the bins. The new soft bit reference levels are determined based on the metric. In one aspect, the metric is how many memory cells have a value for a physical parameter within each bin. The soft bit reference levels may be established based on a target percentage for the bins. In one aspect, the metric is how many unsatisfied counters are within each bin.

A memory device having at least one output predicting a feasibility of whether the memory device will work properly at a different operating condition including a different supply voltage and/or a different operating frequency than the current supply voltage and/or the current operating frequency. A semiconductor device (e.g. a SoC chip) provides a test to either validate or invalidate the feasibility for the memory device to enter such a different operating condition based on read and write operations of the memory device in normal access cycles. The memory device is partitioned with at least a first memory unit and a second memory unit, which can be coupled to different back-bias voltages. This operating condition predicting function can be enabled or disabled by the semiconductor device in real time operation depending on the feasibility test results.

In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.