A test rack includes two or more memory device test boards where each memory device test boards includes two or more memory device test resources. Each of the two or more memory device test boards includes a separate processing device allocated to the memory device test resources of a corresponding memory device test boards. A processing device of a test board detects that a first memory sub-system has engaged with a first memory device test resource of the corresponding memory device test board. The processing device identifies a first test to be performed for a first memory device of the first memory sub-system, where the first test includes one or more first test instructions to be executed in performance of the first test. The processing device causes the one or more first test instructions to be transmitted to the first memory sub-system, where the first test is performed by the one or more first test instructions executing at the first memory sub-system.

A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

A flash memory comprising a first plurality of memory cells, each memory cell of the first plurality of memory cells selectively connected to a first input of a comparator. A second plurality of memory cells selectively connected to a second input of the comparator, wherein a first number of the second plurality of memory cells are in an erased state, wherein a second number of the second plurality of memory cells are in a written state, wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first cell capacitance, and wherein the sum of the first number and the second number is at least three.

In a memory component programmed to operate in a first operating mode and having a page buffer and a fixed-width data interface, N bits of a command/address value are decoded to access one of 2.sup.N columns of data within the page-buffer, with that column of data output via the fixed-width data interface over a first burst interval. If programmed to operate in a second operating mode, M bits of the command/address value are decoded to access a larger column of dataone of 2.sup.M columns of data within the page buffer, where M<Nwith that larger column of data output via the fixed-width data interface over a second burst interval longer than the first burst interval.

In a memory component programmed to operate in a first operating mode and having a page buffer and a fixed-width data interface, N bits of a command/address value are decoded to access one of 2.sup.N columns of data within the page-buffer, with that column of data output via the fixed-width data interface over a first burst interval. If programmed to operate in a second operating mode, M bits of the command/address value are decoded to access a larger column of dataone of 2.sup.M columns of data within the page buffer, where M<Nwith that larger column of data output via the fixed-width data interface over a second burst interval longer than the first burst interval.

A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

A memory control component has control circuitry and a data interface, the data interface to be coupled, via a plurality of data signaling paths, to a respective plurality of memory dies disposed on a memory module. The control circuitry transmits to the memory module a first configuration value that specifies a memory die quantity N that is permitted to range from a first value corresponding to the quantity of the data signaling paths to at least one value less than the first value. Thereafter, the control circuitry transmits a memory read command to the memory module to enable, in accordance with the first configuration value, a quantity N of the memory dies to output read data and enables the data interface to receive the read data via a respective quantity N of the data signaling paths.

A memory control component has control circuitry and a data interface, the data interface to be coupled, via a plurality of data signaling paths, to a respective plurality of memory dies disposed on a memory module. The control circuitry transmits to the memory module a first configuration value that specifies a memory die quantity N that is permitted to range from a first value corresponding to the quantity of the data signaling paths to at least one value less than the first value. Thereafter, the control circuitry transmits a memory read command to the memory module to enable, in accordance with the first configuration value, a quantity N of the memory dies to output read data and enables the data interface to receive the read data via a respective quantity N of the data signaling paths.

A flash memory comprising a first plurality of memory cells, each memory cell of the first plurality of memory cells selectively connected to a first input of a comparator. A second plurality of memory cells selectively connected to a second input of the comparator, wherein a first number of the second plurality of memory cells are in an erased state, wherein a second number of the second plurality of memory cells are in a written state, wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first cell capacitance, and wherein the sum of the first number and the second number is at least three.

A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.