Flash memory with reference voltage generation from a plurality of cells

Abstract

A flash memory comprising a first plurality of memory cells, each memory cell of the first plurality of memory cells selectively connected to a first input of a comparator. A second plurality of memory cells selectively connected to a second input of the comparator, wherein a first number of the second plurality of memory cells are in an erased state, wherein a second number of the second plurality of memory cells are in a written state, wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first cell capacitance, and wherein the sum of the first number and the second number is at least three.

Claims

1. A flash memory comprising: a first plurality of memory cells, each memory cell of the first plurality of memory cells selectively connected to a first input of a comparator; a second plurality of memory cells selectively connected to a second input of the comparator, wherein a first number of the second plurality of memory cells are in an erased state; wherein a second number of the second plurality of memory cells are in a written state; wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first cell capacitance; and wherein a sum of the first number and the second number is at least three.

2. A flash memory according to claim 1, wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first size comprising a first channel length and a first channel width.

3. A flash memory according to claim 1, wherein the first plurality of memory cells and the second plurality of memory cells are distributed in an array, and wherein the second plurality of memory cells are in positions spread out evenly across the array.

4. A flash memory according to claim 1, wherein the second plurality of memory cells is configured to generate a reference voltage.

5. A flash memory according to claim 4, wherein the comparator is configured to compare a first voltage received at the first input with the reference voltage received at the second input.

6. A flash memory according to claim 4, wherein the second plurality of memory cells is configured to generate the reference voltage by integrating a signal current received from each memory cell of the second plurality of memory cells for a predetermined time.

7. A flash memory according to claim 1, comprising a plurality of comparators, wherein the first plurality of memory cells is divided into a first plurality of bitlines, each connected to a respective first input of a respective comparator of the plurality of comparators; and wherein the second plurality of memory cells is divided into a second plurality of bitlines connected in parallel to each respective second input of the plurality of comparators.

8. A method of operating a flash memory, said method comprising: receiving at a first input of a comparator a first signal from a first memory cell of a first plurality of memory cells; receiving at a second input of the comparator a second signal from a second plurality of memory cells, wherein a first number of the second plurality of memory cells are in an erased state; wherein a second number of the second plurality of memory cells are in a written state; wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first cell capacitance; and wherein a sum of the first number and the second number is at least three.

9. A method according to claim 8, wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first size comprising a first channel length and a first channel width.

10. A method according to claim 8, wherein the first plurality of memory cells and the second plurality of memory cells are distributed in an array, and wherein the second plurality of memory cells are in positions spread out evenly across the array.

11. A method according to claim 8, comprising generating the second signal with the second plurality of memory cells, wherein the second signal is a reference voltage.

12. A method according to claim 11, wherein said generating comprises integrating a signal current received from each memory cell of the second plurality of memory cells for a predetermined time.

13. A method according to claim 8, comprising, at the comparator, comparing the first signal and the second signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a known flash memory array structure.

(2) FIG. 2 shows a known digital bus architecture.

(3) FIG. 3 shows a graph illustrating voltage distributions during a memory read operation.

(4) FIG. 4 shows a graph illustrating the effective memory window during a memory read operation.

(5) FIG. 5 shows a diagram illustrating the relationship between memory end of life and the width of a reference voltage distribution.

(6) FIG. 6 shows a diagram illustrating the relationship between memory end of life and the width of a reference voltage distribution which has been narrowed.

(7) FIG. 7(a) shows a digital bus architecture.

(8) FIG. 7(b) shows a digital bus architecture according to an embodiment of the invention.

(9) FIG. 8(a) shows graph illustrating yield loss where a wide reference voltage distribution overlaps with the erased and programmed state voltage distributions.

(10) FIG. 8(b) shows a graph illustrating yield loss where a narrow reference voltage is not centered between the erased and programmed state voltage distributions.

(11) FIG. 9 shows a graph illustrating a narrowed, centered reference voltage distribution obtained using an embodiment of the invention.

DETAILED DESCRIPTION

(12) The present disclosure provides a method to improve memory robustness by reducing the effects of MW.sub.EFF degradation caused by transistor reliability effects under different process, voltage and temperature ranges. This may be achieved by providing a reference voltage V.sub.REF which is generated from a plurality of memory cells in multiple reference bitlines, each cell being in different storage states (i.e. erased or programmed), and each of the plurality of memory cells having the same size (e.g. same channel length and width, and construction and thus the same cell capacitance) as the rest of the memory cells in a memory array.

(13) As described above, there is an inherent variability in the response that different memory cells have when operating under a range of process, voltage and temperature ranges. As the memory ages, this variability increases and this reduces the robustness of the memory as the width of MW.sub.EFF decreases.

(14) The technique used in U.S. Pat. No. 6,687,150 to obtain an average V.sub.REF with a narrow G.sub.REF has been found to not produce a V.sub.REF positioned close to the middle between V.sub.H and V.sub.L. If the center of the V.sub.REF distribution is positioned too far from the middle and too close to V.sub.H or V.sub.L, it does not matter how narrow it is as the memory will still start to fail as soon as there is overlap between the V.sub.REF distribution and the V.sub.H or V.sub.L values. If V.sub.REF is very close to the V.sub.H or V.sub.L values when MW.sub.EFF starts to narrow, end of life is often reached very quickly.

(15) One of the causes of a non-centered V.sub.REF distribution in U.S. Pat. No. 6,687,150 is that the reference cells used to generate V.sub.REF have a different size and thus cell capacitance compared to the cells of the rest of the memory. These differently sized reference cells have different response characteristics compared to the other cells of the array when operating under varying process, voltage and temperature ranges. This causes the center of the V.sub.REF distribution generated by the differently sized reference cells to be positioned at a distance from the middle of the V.sub.TH.sub._.sub.E and V.sub.TH.sub._.sub.P distributions (i.e. the mathematical middle between V.sub.H and V.sub.L). In particular, it will be closer to either V.sub.H or V.sub.L, depending on the operating conditions.

(16) An example of a process variation effect is one that arises as a result of poly etching techniques used during manufacture. In particular, tolerated manufacturing variations caused by the poly etching technique creates variations in the effective channel length of different cells (and thus how they respond under different conditions), the shorter the length, the stronger the influence that a manufacturing variation can have on cell response. Because reference cells have a different channel length in U.S. Pat. No. 6,687,150 compared to the memory cells, the influence that the process variation has on the response of the shorter length cells is different to the influence that the variations have on the longer length cells. Similarly, other manufacturing techniques which permit tolerated manufacturing variations may suffer from similar types of process dependencies.

(17) An example of a voltage variation effect is that the threshold voltage of a transistor depends on its channel length. Different channel lengths cause different voltage dependencies (i.e. different response characteristics under different voltages).

(18) This disadvantage may be able to be overcome by generating a V.sub.REF distribution not from separate reference cells of greater cell capacitance, but instead from memory cells taken from the rest of the cells which make up the memory array and which thus have the same size (e.g. channel length, width and construction and thus cell capacitance) as the other cells in the array. This results in all of the cells having identical process, voltage and temperature dependency. This contrasts with the differently sized reference cells of U.S. Pat. No. 6,687,150. As described above, by using memory cells having the same cell size (e.g. channel length, width and construction and thus capacitance) as the other array cells to generate the V.sub.REF distribution, it will mean that both the reference cells and the cells being read will have a much closer dependency and operating response to varying process, voltage and temperature ranges than reference cells with a different cell size and thus capacitance. As all the cells (i.e. reference cells and the other cells in the array) are the same size, they will inherently respond in the same way to different operating conditions and the V.sub.REF distribution will be far closer to the actual middle of MW.sub.EFF i.e. the mathematical middle in between V.sub.H and V.sub.L across a much larger set of process, voltage and temperature ranges.

(19) The above described technique may be able to be implemented by generating a V.sub.REF distribution using an average calculated from memory cells selected so as to be spread out evenly across the memory array, and which are in a combination of erased and programmed (i.e. written) states. The total number of cells from which the average is calculated is three or more. This contrasts with the technique used in U.S. Patent Application Publication No. 2011/194330, which generates an average V.sub.REF using only two single cells, positioned at single points in the array (i.e. having single point characteristics which depend on the position they have in the array), one in an erased state and one in a written/programmed state. Whilst the technique used in U.S. Patent Application Publication No. 2011/194330 may produce a narrow V.sub.REF distribution, it cannot compensate for the scenario where there is an unequal distribution of erased and programmed state cells around the memory array. The unequal distribution of cells in different states around a memory array results in a shift of the positions and/or widths of the V.sub.TH.sub._.sub.E and V.sub.TH.sub._.sub.P distributions. An example reason for this is that tolerated manufacturing process variations may have resulted in certain areas of the array having higher channel lengths compared to other areas, thus having different response characteristics. Thus, even if V.sub.REF is narrow, if the positions and widths of the V.sub.TH.sub._.sub.E and V.sub.TH.sub._.sub.P distributions have shifted due to an unequal distribution to such an extent that they overlap with V.sub.REF, the memory may still start to fail and reach end of life sooner. Generating a V.sub.REF distribution using an average calculated from multiple reference bitlines made up of a plurality of memory cells taken from positions spread out evenly across the array overcomes this disadvantage.

(20) The above described techniques may be able to be further improved by changing the ratio of erased to programmed state cells in the plurality of memory cells used to generate the V.sub.REF distribution. This ratio can be defined during a memory array characterization step (e.g. during array manufacture and calibration). Once the ratio is defined it can be used during all write operations. As described above, the voltages that make up the V.sub.TH.sub._.sub.E distribution (i.e. erased cells) are lower than the voltages that make up the V.sub.TH.sub._.sub.P distribution (i.e. written/programmed cells). By changing the ratio, the V.sub.REF distribution (which is generated as an average of the higher V.sub.TH.sub._.sub.P voltages and lower V.sub.TH.sub._.sub.E) will have its center position shifted higher or lower as required. By including more erased cells, the center of the V.sub.REF distribution will be shifted closer to V.sub.L. In contrast, by including more programmed (i.e. written state) cells, the center of the V.sub.REF distribution will be shifted closer to V.sub.H.

(21) The above described techniques each contribute individually and together to enable the center of the generated V.sub.REF distribution to be positioned much closer to the mathematical middle between V.sub.H or V.sub.L than is possible with the technique of U.S. Pat. No. 6,687,150 while simultaneously providing the means to shift the center of the V.sub.REF distribution if necessary, to respond to unequal distributions of erased and written cells which is not possible using the technique of U.S. Patent Application Publication No. 2011/194330.

(22) The effect of the above described techniques is illustrated in FIGS. 5 and 6. In graph 500, the reference distribution 501 is relatively wide so overlaps much sooner with the highest voltage in the V.sub.TH.sub._E distribution 502 and the lowest voltage in the V.sub.TH.sub._.sub.P distribution 503, thus reaching end of life much sooner. Additionally, whilst not shown in FIG. 5 or 6, if the reference distribution is not centered, overlap could also occur sooner, resulting in reaching end of life sooner.

(23) In contrast, graph 600 shows where end of life might occur with a narrower reference distribution 601 which is more closely centered than in graph 500. Even though MW.sub.EFF decreases in size over time, the reference distribution 601 is narrow enough and centered enough to fit in between the highest voltage in the V.sub.TH.sub._.sub.E distribution 602 and the lowest voltage in the V.sub.TH.sub._.sub.P distribution 603 for a much greater period of time. In other words the time between the start of life of the memory and end of life is increased, helping to enable the memory designer to meet a chosen design goal more easily.

(24) FIGS. 7(a) and (b) illustrate the difference between a known digital bus 700 and a digital bus 701 according to an embodiment of the invention. FIG. 7(a) is identical to the known digital bus 201 shown in FIG. 2. FIG. 7(b) shows a digital bus 701 having a reference block 702 configured to receive signals from at least three memory cells selected from evenly distributed positions around the array. A first number of the selected memory cells are in an erased state, and a second number of the memory cells are in a programmed state. The ratio of the first number to the second number is a factor in determining the center position of the V.sub.REF distribution. The ratio can be changed (e.g. during an array characterization step during manufacture and calibration) to shift the center position of the V.sub.REF distribution. In order to change the ratio, a write operation can be performed on the memory cells of the reference block. If the position of V.sub.REF is to be shifted higher, write operations may be performed such that more cells in the reference memory block are set to be in their written state. Conversely, if the position of V.sub.REF is to be shifted lower, write operations may be performed such that more cells in the reference memory block are set to be in their erased state. The total number of selected cells is a factor in determining the width of the V.sub.REF distribution, as will be described below. It is envisaged that the total number of cells in the reference memory block and the ratio of written cells to erased cells is fixed during an array characterization step during manufacture and calibration. The output from the reference member block 702 is the input into each of the comparators of the digital bus 701.

(25) FIGS. 8(a) and 8(b) show graphs 800, 801 of voltage distributions obtained using known techniques. Graph 800 in FIG. 8(a) shows V.sub.TH.sub._.sub.E, V.sub.TH.sub._.sub.P, and V.sub.REF distributions 802, 803, 804 which are similar to the distributions shown in FIG. 3 and which indicate a yield loss 805 (i.e. failed memory read operations) where the distributions overlap. Graph 801 in FIG. 8(b) shows V.sub.TH.sub._.sub.E, V.sub.TH.sub._.sub.P, and V.sub.REF distributions 806, 807, 808 where the V.sub.REF distribution 808 is narrowed but is not centered in the middle between V.sub.H or V.sub.L. Rather, it is positioned too close to the edge of the V.sub.TH.sub._.sub.E distribution 806, resulting in overlap and yield loss 809.

(26) In contrast, FIG. 9 shows a graph 900 of V.sub.TH.sub._.sub.E, V.sub.TH.sub._.sub.P, and V.sub.REF distributions 901, 902, 9034 obtained using the above described techniques. The V.sub.REF distribution 903 is narrowed and is centered the between V.sub.TH.sub._.sub.E, V.sub.TH.sub._.sub.P distributions 901, 902 without overlap, thus guaranteeing successful read operations without yield loss.

(27) A flash memory according to the above described techniques comprises a first plurality of memory cells, each memory cell of the first plurality of memory cells selectively connected to a first input of a comparator, where selectively connected may be understood to mean that each cell may be addressed using an X,Y decoder and read accordingly. A second plurality of memory cells selectively connected to a second input of the comparator. In contrast to the first plurality of memory cells, the second plurality of memory cells are all connected to all of the second inputs of each of the comparators of the memory (where multiple comparators are present). A first number of the second plurality of memory cells are in an erased state. A second number of the second plurality of memory cells are in a written state. Each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has the same cell size and thus capacitance. The sum of the first number and the second number is at least three. Each of the memory cells of the first plurality of memory cells is capable of generating a first signal to be received at the first input of the comparator (i.e. the signal associated with the cell(s) being read). The second plurality of memory cells together generate a second signal to be received at the second input of the comparator (i.e. the reference voltage signal).

(28) It is envisaged that all of the memory cells of the second plurality of memory cells in the second plurality of memory cells are in at least an erased or written state. However, it is also possible to implement the system and method where this is true of only a majority (but not all) of the memory cells of the second plurality of memory cells. This allows the above described techniques to be combined with existing techniques to produce a hybrid system.

(29) As described above, during a read operation, a digital bit is detected by way of a comparison, at the comparator, of the reference voltage signal with an input voltage signal received from the memory cell being read. As there are multiple comparators, multiple digital bits (i.e. N digital bits) can be detected at the same time. As described above, due to inherent variability in response under different process, temperature and voltage operating conditions, both the reference signal and the N input signal voltages will be distributed about a respective mean and have a respective standard deviation

(30) Each of the N signal voltages is determined by way of integration of the signal current (I.sub.H or I.sub.L, depending on what state a given cell is in) over capacitance, for a predetermined time, which generates a voltage at the end of the integration time associated with the cell being read.

(31) The reference voltage V.sub.REF is determined in the same manner by taking the integrated current over integrated capacitance for each of the memory cells selected to be reference cells, and taking an average of the output values. As described above, the memory cells selected to be reference cells are selected from positions spread evenly around the array, being in a combination of erased and programmed states, and are three or more in number. In the extreme case, where there are only three, the average will be heavily shifted towards one side as the number of reference memory cells in one state will be double or half that of the number of cells in the other state (e.g. two written state cells and one erased state cell will shift the V.sub.REF center position significantly towards the mean of V.sub.TH.sub._.sub.P). As will be described below, whilst this may not be useful in all cases, the greater possible shift of the reference voltage means it can still be used to shift the center position a very large amount without having to provide a separate biasing means. Conversely, at the other extreme, a very large number of memory cells in different states selected to be reference cells provides a higher granularity of control for making small, subtle shifts to the center position of V.sub.REF.

(32) If the input signal voltage is higher than the reference voltage, the comparator outputs that the cell is in its programmed state (i.e. a digital 1). If the generated signal voltage is lower than the reference voltage, the comparator outputs that the cell is in its erased state (i.e. a digital 0). It is assumed because of the mismatch variation of the signal current and capacitance (i.e. the signal currents and cell capacitances also have some variability so are also distributions with a respective mean and standard deviation) that the integrated signal voltages would, in practice, have mismatched distributions. In other words, the width of the V.sub.TH.sub._.sub.E and V.sub.TH.sub._.sub.P distributions is not necessarily the same in practice. However, it is assumed for this explanation that both distributions have the same standard deviation value .

(33) The ratio of erased state cells to programmed state cells may be adjusted during manufacture with a write operation to change the width and position of the V.sub.REF distribution to match whatever variations are present in the V.sub.TH.sub._.sub.E and V.sub.TH.sub._.sub.P distributions so as to minimize any overlap, thus providing a greater degree of control during a memory array characterization step during manufacture.

(34) As a backup option to act as a further degree of freedom to assist in the positioning of the center of V.sub.REF, a suitable scaling (also known as a biasing) factor may be applied to V.sub.REF. The purpose of the scaling factor can be to shift the center position of V.sub.REF so that it falls between V.sub.H and V.sub.L. In practice this can be done by scaling the reference capacitance or current.

(35) As described above, the reference block consists of multiple bitlines, described herein as reference bitlines but which are otherwise the same as the bitlines of the rest of the array. These are connected M times in parallel to the N comparators (see FIG. 7(b)). In particular, the outputs of the reference bitlines are all connected to each other and to the reference input of each of the comparators such that the reference bitlines are said to be connected in parallel to each respective reference input of the plurality of comparators. The effect of this is to narrow the standard deviation .sub.REF of the V.sub.REF distribution by a factor of M i.e. the V.sub.REF standard deviation is now .sub.REF/M. The greater the value of M, the narrower the V.sub.REF distribution will become. In FIG. 7(b), the reference bitlines are labelled as running from M1 to 0.

(36) As the width of the V.sub.REF distribution gets narrower, the time it takes to reach end of life is extended as memory cells can continue to be read successfully for longer as the narrower V.sub.REF distribution does not overlap with V.sub.H or V.sub.L until a longer time has passed and a greater degree of degradation has occurred.

(37) Further, the more reference bitlines and thus memory cells that are in the reference block, the less effect parasitic capacitances and die-to-die variations (e.g. minor structural differences within manufacturing tolerances) will have on the operation of the memory because these are averaged out.

(38) An additional advantage of the above described techniques is that calibration time of a memory may be significantly reduced as it is much easier and quicker to adjust the V.sub.REF distribution position and width than is possible using known techniques. This decreases total production time and cost without sacrificing performance of the memory with regard to process, voltage and temperature ranges, data retention and susceptibility to disturbance effects.

(39) The system and method are of particular applicability to cases where the V.sub.TH.sub._.sub.E and V.sub.TH.sub._.sub.P distributions of the memory cells are very wide such that the separation between V.sub.TH.sub._.sub.E and V.sub.TH.sub._.sub.P is very small and MW.sub.EFF is very narrow.

(40) As described above, the ability to shift the center position of the V.sub.REF distribution by changing the ratio of erased to programmed cells in the plurality of cells used to generate the V.sub.REF distribution has been discussed in connection with overcoming the effects of unequal distributions of erased and programmed cells in an array. However, the same technique can also be used to compensate for any other technological effects such as variations in process, voltage and temperature ranges which result from manufacturing techniques or operation of the array and which results in a change in position and/or width of the V.sub.TH.sub._.sub.E and V.sub.TH.sub._.sub.P distributions. In particular, the above described techniques provide the ability to always position the center of the V.sub.REF distribution exactly in the middle of the V.sub.TH.sub._.sub.E and V.sub.TH.sub._.sub.P distributions by providing an adjustable center position of the V.sub.REF distribution.

(41) Further, as described above, the memory cells used to generate V.sub.REF are selected to be distributed evenly across the memory array. One reason for this is that cell position is a factor which contributes to cell response under different operating conditions (i.e. varying process, temperature and voltage ranges). Cells which are positioned close to each other on a die are more likely to have a similar operational response compared to cells which are positioned far away on a die. One reason for this is that minor manufacturing defects are likely to be local to certain positions and will thus affect local cells equally. By using a plurality of cells selected evenly from across different positions in the array (and thus across the die), the response variation of memory cells in proximity to the selected reference cells are inherently taken into account when determining an average V.sub.REF. The term spread evenly means that the selected cells are positioned at approximately equal distances from each other in the array.

(42) If parts of a die are known to have a specific effect on cell response, it is also possible to select a plurality of cells which are less evenly distributed across an array (e.g. to avoid an area). For example, reference memory cells may be selected to provide a V.sub.REF which is more strongly correlated with particular sections of the array. This provides another degree of freedom when positioning the center of the V.sub.REF distribution.

(43) Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.