An integrated circuit includes a built-in-self-test circuit that generates output test signals and a circuit tested by the built-in-self-test circuit. The circuit tested by the built-in-self-test circuit generates test results in response to the output test signals during a test. Pipeline register circuits are coupled together to form a signal path for transmitting the output test signals from the built-in-self-test circuit to the circuit tested by the built-in-self-test circuit. A functional circuit block is located in a reserved die area of the integrated circuit. The signal path is routed around the reserved die area to the circuit tested by the built-in-self-test circuit. At least a subset of the pipeline register circuits are located adjacent to at least two sides of the reserved die area.

An integrated circuit includes a built-in-self-test circuit that generates output test signals and a circuit tested by the built-in-self-test circuit. The circuit tested by the built-in-self-test circuit generates test results in response to the output test signals during a test. Pipeline register circuits are coupled together to form a signal path for transmitting the output test signals from the built-in-self-test circuit to the circuit tested by the built-in-self-test circuit. A functional circuit block is located in a reserved die area of the integrated circuit. The signal path is routed around the reserved die area to the circuit tested by the built-in-self-test circuit. At least a subset of the pipeline register circuits are located adjacent to at least two sides of the reserved die area.

A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.

A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.

A refresh time detection circuit and a semiconductor device including the same may be provided. The refresh time detection circuit may include a code generator configured to generate a code signal for detecting a refresh time. The refresh time detection circuit may include a latch circuit configured to generate a latch signal by latching the code signal according to a fail signal, and generate a pre-code signal and a post-code signal by latching each latch signal according to a pre-enable signal and a post-enable signal. The refresh time detection circuit may include a subtractor configured to output a refresh detection signal by performing subtraction between the pre-code signal and the post-code signal. The refresh time detection circuit may include a comparator configured to generate a detection signal by comparing the refresh detection signal with an offset signal based on the post-enable signal.

A refresh time detection circuit and a semiconductor device including the same may be provided. The refresh time detection circuit may include a code generator configured to generate a code signal for detecting a refresh time. The refresh time detection circuit may include a latch circuit configured to generate a latch signal by latching the code signal according to a fail signal, and generate a pre-code signal and a post-code signal by latching each latch signal according to a pre-enable signal and a post-enable signal. The refresh time detection circuit may include a subtractor configured to output a refresh detection signal by performing subtraction between the pre-code signal and the post-code signal. The refresh time detection circuit may include a comparator configured to generate a detection signal by comparing the refresh detection signal with an offset signal based on the post-enable signal.

A semiconductor apparatus may include: a data storage group including first to eight data storage areas; a first channel select pad configured to transmit a first channel select signal to the first and third data storage areas; a second channel select pad configured to transmit a second channel select signal to the second and fourth data storage areas; a third channel select pad configured to transmit the first channel select signal to the sixth and eighth data storage areas; a fourth channel select pad configured to transmit the second channel select signal to the fifth and seventh data storage areas; a first clock enable pad configured to transmit a first clock enable signal to the first and third data storage areas; a second clock enable pad configured to transmit a second clock enable signal to the second and fourth data storage areas; a third clock enable pad configured to transmit the first clock enable signal to the fifth and seventh data storage areas; and a fourth clock enable pad configured to transmit the second clock enable signal to the sixth and eighth data storage areas.

A semiconductor apparatus may include: a data storage group including first to eight data storage areas; a first channel select pad configured to transmit a first channel select signal to the first and third data storage areas; a second channel select pad configured to transmit a second channel select signal to the second and fourth data storage areas; a third channel select pad configured to transmit the first channel select signal to the sixth and eighth data storage areas; a fourth channel select pad configured to transmit the second channel select signal to the fifth and seventh data storage areas; a first clock enable pad configured to transmit a first clock enable signal to the first and third data storage areas; a second clock enable pad configured to transmit a second clock enable signal to the second and fourth data storage areas; a third clock enable pad configured to transmit the first clock enable signal to the fifth and seventh data storage areas; and a fourth clock enable pad configured to transmit the second clock enable signal to the sixth and eighth data storage areas.

A method for detecting a reading error of a datum in memory. A binary word which is representative of the datum and an error correcting or detecting code is read by: reading a first part of the binary word stored at a first address in a first memory circuit; and reading a second part of the binary word stored at a second address in a second memory circuit. The first and second parts read from the first and second memory circuits, respectively, are concatenated to form a read binary word. The datum is then obtained by removing the error correcting or detecting code from the read binary word. A new error correcting or detecting code is calculated from the obtained datum and compared to the removed error correcting or detecting code to detect error in the obtained datum.

An IC includes an array of processor units, arranged in two or more subarrays. A subarray has a test generator, a multiplexer to apply a test vector to a datapath, and a test result output. It includes one or more processor units. A test result compressor is coupled with an output of the datapath, and compresses output data to obtain a test signature, which it stores in a signature register. The signature register is legible from outside the subarray. The datapath includes one or more memories and one or more ALUs. Test data travels through the full datapath, including the memories and the ALUs. ALU control registers are overridden during test to ensure a testable datapath.