A semiconductor apparatus including a semiconductor chip is disclosed. The semiconductor chip includes a modular region and a test circuit. The modular region includes a plurality of modular areas each including a memory cell array with redundant bit lines and a peripheral memory area storing at least redundant addresses. The test circuit retrieves the redundant addresses intrinsic to the semiconductor chip. The distribution of the redundant addresses are randomly formed related to a part or a whole of the modular area of the modular region. The test circuit outputs a random number generated from physical properties intrinsic to the semiconductor chip according to a specification code received from a physical-chip-identification measuring device.

A memory device includes a first memory block suitable for transmitting and receiving signals through a first channel, a second memory block suitable for transmitting and receiving signals through a second channel, and a test control unit suitable for applying a first command signal among a plurality of command signals to the first and second channels at different values, while applying the plurality of command signals from an exterior of the memory device to the first and second channels in a test operation, wherein the first command signal distinguishes write and read operations of the first and second memory blocks, wherein, when the first memory block performs a read operation in the test operation, the second memory block performs a write operation, and data outputted from the first memory block is inputted to the second memory block.

A memory device includes a first memory block suitable for transmitting and receiving signals through a first channel, a second memory block suitable for transmitting and receiving signals through a second channel, and a test control unit suitable for applying a first command signal among a plurality of command signals to the first and second channels at different values, while applying the plurality of command signals from an exterior of the memory device to the first and second channels in a test operation, wherein the first command signal distinguishes write and read operations of the first and second memory blocks, wherein, when the first memory block performs a read operation in the test operation, the second memory block performs a write operation, and data outputted from the first memory block is inputted to the second memory block.

A default read operation is performed on a page using a default read voltage set to generate default raw data. If error bits of the default raw data are not corrected, a plurality of low-level read operations is performed on the page using a plurality of read voltage sets to generate a plurality of low-level raw data. Each read voltage set is different from the default voltage set. A read voltage set is selected from the plurality of read voltage sets as a starting voltage set, according to each low-level raw data. A high-level read operation using the selected starting voltage set is performed on the page to generate high-level raw data.

A default read operation is performed on a page using a default read voltage set to generate default raw data. If error bits of the default raw data are not corrected, a plurality of low-level read operations is performed on the page using a plurality of read voltage sets to generate a plurality of low-level raw data. Each read voltage set is different from the default voltage set. A read voltage set is selected from the plurality of read voltage sets as a starting voltage set, according to each low-level raw data. A high-level read operation using the selected starting voltage set is performed on the page to generate high-level raw data.

Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor, a register storing timing information, and an arbiter circuit configured to determine whether the resistor is available based, at least in part, on the timing information stored in the register. The timing information stored in the register of each respective chip of the plurality of chips is unique to the respective chip among the plurality of chips.

An integrated circuit is provided for self-repair of a memory array. The circuit includes first word lines coupled to first memory rows of the memory array, one first word line for each bit of a line address word, second word lines coupled to one or more spare memory rows of the memory array. Repair configuration data is stored in memory cells within the integrated circuit to direct memory accesses to spare memory rows rather than dysfunctional first memory rows. A memory cell may be based on a correlated electron switch (CES). A built-in self-test circuit is provided to facilitate setting of repair configuration data. The repair data may be reconfigurable, enabling operating margins to be improved by testing under various operating conditions.

A semiconductor device may include a refresh counter configured to output a plurality of refresh addresses by counting a refresh signal; a check signal generator configured to generate a check signal according to a logic level of any one specific refresh address among the plurality of refresh addresses during a refresh operation, and output the check signal in response to a redundancy check pulse signal; a redundancy checker configured to store information on whether a redundancy cell was used, in response to the check signal, the redundancy check pulse signal and the plurality of refresh addresses, and output a word line control signal according to whether the redundancy cell was used; and a refresh controller configured to control a row address for selectively enabling a word line and a redundancy word line of a cell array in response to the word line control signal.

A device is disclosed for testing a memory, in which the memory includes a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first response in responses of the first memory circuit, and the first memory circuit is configured to store a second response of responses of the second memory circuit. The device includes a comparing circuit and a maximum hamming distance generating circuit. The comparing circuit is configured to compare the first response with the responses of the first memory circuit, and configured to compare the second response with the responses of the second memory circuit, to generate comparing results. The maximum hamming distance generating circuit is configured to generate a maximum hamming distance according to the comparing results.

A device is disclosed for testing a memory, in which the memory includes a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first response in responses of the first memory circuit, and the first memory circuit is configured to store a second response of responses of the second memory circuit. The device includes a comparing circuit and a maximum hamming distance generating circuit. The comparing circuit is configured to compare the first response with the responses of the first memory circuit, and configured to compare the second response with the responses of the second memory circuit, to generate comparing results. The maximum hamming distance generating circuit is configured to generate a maximum hamming distance according to the comparing results.