Apparatuses, systems, and methods related to determination of a match between data values stored by three or more arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by three arrays selected from the plurality to determine whether there is a match between the data values stored by the three arrays. The apparatus further includes an output component configured to output data values of one of two arrays of the three arrays responsive to determination of the match between the data values stored by the two arrays.

Apparatuses, systems, and methods related to determination of a match between data values stored by three or more arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by three arrays selected from the plurality to determine whether there is a match between the data values stored by the three arrays. The apparatus further includes an output component configured to output data values of one of two arrays of the three arrays responsive to determination of the match between the data values stored by the two arrays.

A method to manufacture a semiconductor device includes: bonding a first wafer and a second wafer to be stacked vertically with one another, in which the first wafer provides a plurality of memory components and the second wafer provides a control circuit; forming a plurality of input/output channels on a surface of one of the first and second wafers; and cutting the bonded first and second wafers into a plurality of dices; wherein a plurality of first conductive contacts in the first wafer are electrically connected to the control circuit and the first conductive contacts in combinations with a plurality of first conductive vias in the first wafer form a plurality of transmission channels through which the control circuit is capable to access the memory components.

A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.

A memory device comprises a memory array that includes memory cells and a memory controller operatively coupled to the memory array. The memory controller includes an oscillator circuit, internal memory, a processor core coupled to the oscillator circuit and the internal memory, and configured to load operating firmware during a boot phase of the memory device, voltage detector circuitry configured to detect a decrease in a circuit supply voltage of the memory controller during the boot phase, and logic circuitry configured to halt operation of the oscillator circuit and power down the processor core and the internal memory during the boot phase in a low power mode in response to detecting the decrease in the circuit supply voltage.

A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and a power management component, operatively coupled with the memory array. The power management component sends a test value to one or more other power management components on one or more other memory dies of the plurality of memory dies and receives one or more other test values from the one or more other power management components. The power management component compares the test value and the one or more other test values to a set of expected values, and responsive to the test value and the one or more other test values matching the set of expected values, determines that signal connections between the power management component and the one or more other power management components are functional.

In a described example, an integrated circuit (IC) includes a repairable memory system. A repair controller is coupled to the repairable memory system. The repair controller includes compression logic configured to encode memory repair code data for a respective instance of the repairable memory system and provide compressed repair data. A non-volatile memory controller is coupled to the repair controller and to non-volatile memory. The non-volatile memory controller is configured to transfer the compressed repair data to the non-volatile memory for storage.

A method for detecting a reading error of a datum in memory. A binary word which is representative of the datum and an error correcting or detecting code is read by: reading a first part of the binary word stored at a first address in a first memory circuit; and reading a second part of the binary word stored at a second address in a second memory circuit. The first and second parts read from the first and second memory circuits, respectively, are concatenated to form a read binary word. The datum is then obtained by removing the error correcting or detecting code from the read binary word. A new error correcting or detecting code is calculated from the obtained datum and compared to the removed error correcting or detecting code to detect error in the obtained datum.

A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.

A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.