Techniques for testing an integrated circuit (IC) are disclosed. A controller in the IC retrieves first testing data from a first memory in the IC. The controller transmits the first testing data to a first built-in self-test (BIST) core. The controller receives a response from the first BIST core, relating to a test at the first BIST core using the first testing data. The controller determines a status of the test relating to the IC based on the response.

Disclosed herein is a method of operating a system in a test mode. When the test mode is an ATPG test mode, the method includes beginning stuck-at testing by setting a scan control signal to a logic one, setting a transition mode signal to a logic 0, and initializing FIFO buffer for ATPG test mode. The FIFO buffer is initialized for ATPG test mode by setting a scan reset signal to a logic 0 to place a write data register and a read data register associated with the FIFO buffer into a reset state, enabling latches of the FIFO buffer using an external enable signal, removing the external enable signal to cause the latches to latch, and setting the scan reset signal to a logic 1 to release the write data register and the read data register from the reset state, while not clocking the write data register.

A semiconductor memory device includes a memory and a memory controller configured to control the memory. The memory controller includes a normal operation control part and a repair part. The normal operation control part is configured to control a normal operation of the memory and includes a plurality of storage spaces used while the normal operation is controlled. The repair part is configured to control a repair operation of the memory and stores faulty addresses detected while the repair operation is controlled into the plurality of storage spaces included in the normal operation control part.

A method to manufacture a semiconductor device includes: bonding a first wafer and a second wafer to be stacked vertically with one another, in which the first wafer provides a plurality of memory components and the second wafer provides a control circuit; forming a plurality of input/output channels on a surface of one of the first and second wafers; and cutting the bonded first and second wafers into a plurality of dices; wherein a plurality of first conductive contacts in the first wafer are electrically connected to the control circuit and the first conductive contacts in combinations with a plurality of first conductive vias in the first wafer form a plurality of transmission channels through which the control circuit is capable to access the memory components.

A method for error correction comprises receiving data at a first device, and decoding, by decoder circuitry of the first device, the data. Decoding the data comprises determining a first error location within the data, and determining a first error magnitude within the data in parallel with determining the first error location. Decoding the data further comprises performing error correction to generate the decoded data based on the first error location and the first error magnitude. The method further comprises transmitting the decoded data to a second device.

A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells.

A semiconductor device may include a syndrome generation circuit and a failure detection circuit. The syndrome generation circuit may generate a syndrome signal corresponding to a pattern of an output data signal. The failure detection circuit may detect the syndrome signal and sequentially store the syndrome signal to generate a first syndrome signal and a second syndrome signal if an error is detected from the syndrome signal. The failure detection circuit may generate a failure detection signal which is enabled if a logic level combination of the first syndrome signal is different from a logic level combination of the second syndrome signal.

An integrated circuit includes a drivability control circuit and a data output circuit. The drivability control circuit is configured to generate a drivability control signal based on data patterns of a plurality of pieces of data. The data output circuit is configured to control drivability, which is reflected to each of the plurality of pieces of data, based on the drivability control signal.

A memory controller includes a clock delay generator, a set of flip-flops, and a control circuit, and is connected to a processor and a memory. The clock delay generator receives a clock signal from the processor, delays the clock signal by a set of delay time intervals, and generates a set of delayed clock signals. The flip-flops receive a test pattern and read data from the memory, sample the test pattern and the read data based on the delayed clock signals, and generate a set of sampled test patterns and a set of sampled read data. The control circuit identifies a sampled test pattern that is equal to the test pattern and the corresponding delayed clock signal as a read clock signal, and outputs the sampled read data that corresponds to the (delayed) read clock signal.

Apparatuses and methods of sharing error correction memory on an interface chip are described. An example apparatus includes: at least one memory chip having a plurality of first memory cells and an interface chip coupled to the at least one memory chip and having a control circuit and a storage area. The control circuit detects one or more defective memory cells of the first memory cells of the at least one memory chip. The control circuit further stores first defective address information of the one or more defective memory cells of the first memory cells into the storage area. The interface chip responds to the first defective address information and an access request to access the storage area in place of the at least one memory chip when the access request has been provided with respect to the one or more defective memory cells of the first memory cells.