Disclosed is a system that comprises a memory device comprising a plurality of memory planes and a processing device, operatively coupled with the memory device, to perform operations that include, generating a block stripe of the memory device, wherein the block stripe comprises a plurality of blocks arranged across the plurality of memory planes; determining that a first block of the plurality of blocks of the block stripe is associated with an error condition, wherein the first block is associated with a first plane of the plurality of planes; and responsive to determining that the first block of the plurality of blocks of the block stripe is associated with the error condition, performing an error recovery operation on the plurality of blocks to replace the first block with a replacement block in the block stripe.

A method to manufacture a semiconductor device includes: bonding a first wafer and a second wafer to be stacked vertically with one another, in which the first wafer provides a plurality of memory components and the second wafer provides a control circuit; forming a plurality of input/output channels on a surface of one of the first and second wafers; and cutting the bonded first and second wafers into a plurality of dices; wherein a plurality of first conductive contacts in the first wafer are electrically connected to the control circuit and the first conductive contacts in combinations with a plurality of first conductive vias in the first wafer form a plurality of transmission channels through which the control circuit is capable to access the memory components.

A memory device includes a data pad; a read circuit outputting read or test data to the data pad according to a read timing signal and a read command; a write circuit receiving write data through the data pad according to a write timing signal; a test register circuit performing a preset operation on data and storing the data, and transferring the stored data as the test data in response to the read command, during a first test mode; a data compression circuit generating a test output signal by compressing the test data and outputting the test output signal to a first test output pad, during the first test mode; and a timing control circuit generating, according to first to third output control signals, the read timing signal and generating the write timing signal by delaying the read timing signal, during the first test mode.

A system includes a plurality of memory dice and a processing device coupled to the plurality of memory dice. The processing device is to determine whether an error correcting code (ECC) check of ECC-protected data read from a die of the plurality of memory dice results in detecting an error. In response to detecting the error from the ECC-protected data, the processing device performs a confirmation check that the error is a result of a defect in the die. In response to the confirmation check confirming the die is defective, the processing device ignores a temperature value from the die when determining whether to trigger a thermal-related operation.

A system includes a plurality of memory dice and a processing device coupled to the plurality of memory dice. The processing device is to determine whether an error correcting code (ECC) check of ECC-protected data read from a die of the plurality of memory dice results in detecting an error. In response to detecting the error from the ECC-protected data, the processing device performs a confirmation check that the error is a result of a defect in the die. In response to the confirmation check confirming the die is defective, the processing device ignores a temperature value from the die when determining whether to trigger a thermal-related operation.

A processing device receives a request to write data to a memory device. The processing device generates a codeword based on the data. The codeword comprises the data and error correction code. The processing device generates a compressed codeword by compressing the codeword. The processing device stores the compressed codeword on a page of the memory device.

Embodiments of the present disclosure relate to solutions for introducing personalization data in nonvolatile memories of a plurality of integrated circuits, comprising writing in the nonvolatile memory of a given integrated circuit a static data image, corresponding to an invariant part of nonvolatile memory common to the plurality of integrated circuits, and a personalization data image representing data specific to the given integrated circuit.

A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

A semiconductor memory device includes: a plurality of memory blocks; a plurality of bit-line sense amplifiers shared by neighboring memory blocks among the plurality of the memory blocks, and suitable for sensing and amplifying data read from memory cells coupled to activated word lines through bit lines, and outputting the amplified data through a plurality of segment data lines; a word line driver suitable for activating word lines of memory blocks that do not share the bit-line sense amplifiers during a test mode; and a weak cell detection circuit suitable for compressing the amplified data transferred through the plurality of the segment data lines for generating compressed data and detecting a weak cell based on the compressed data during the test mode.

A semiconductor memory device includes: a plurality of memory blocks; a plurality of bit-line sense amplifiers shared by neighboring memory blocks among the plurality of the memory blocks, and suitable for sensing and amplifying data read from memory cells coupled to activated word lines through bit lines, and outputting the amplified data through a plurality of segment data lines; a word line driver suitable for activating word lines of memory blocks that do not share the bit-line sense amplifiers during a test mode; and a weak cell detection circuit suitable for compressing the amplified data transferred through the plurality of the segment data lines for generating compressed data and detecting a weak cell based on the compressed data during the test mode.