Patent classifications
G01R31/2877
Inspection device and method for operating inspection device
An inspection device according to an embodiment can conduct high temperature inspection and low temperature inspection on an object to be inspected. The inspection device includes an inspection chamber in which inspection is conducted on the object; a dry air supply section that is connected to the inspection chamber via a first valve and that is configured to supply dry air into the inspection chamber; a dew point meter that is connected to the inspection chamber via a second valve and that is configured to measure a dew point in the inspection chamber; and a bypass pipe connecting the dry air supply section and the dew point meter via a third valve.
Prober with cooling mechanism for directly cooling a device under test
Prober for a test system for testing a device under test is disclosed. In one example, the prober comprises a chuck configured for carrying the device under test, a transport circuitry for transporting electric signals to and/or away from the device under test. A cooling unit is directly thermally coupled with the device under test and configured for cooling the device under test at a main surface of the device under test facing the chuck.
COOLANT SUPPLYING APPARATUS, AND TEMPERATURE CONTROLLING APPARATUS AND TEST HANDLER INCLUDING THE SAME
A coolant supplying apparatus, which is configured to prevent dew condensation from being generated in a supply of coolant, and a temperature controlling apparatus and a test handler including the same are provided. The coolant supplying apparatus includes a housing having an outlet, a coolant spraying part arranged inside the housing and configured to discharge coolant around the outlet of the housing, and a dry air injection part configured to inject dry air into the housing.
SYSTEM AND METHOD OF TESTING A SEMICONDUCTOR DEVICE
A system for testing a semiconductor may include a transfer chamber, at least one loadlock chamber and at least one test chamber. The transfer chamber may include a plurality of sidewalls. The loadlock chamber may be arranged on a first sidewall of the sidewalls of the transfer chamber. The loadlock chamber may include a carrier configured to receive a plurality of wafers. The test chamber may be arranged on a second sidewall of the sidewalls of the transfer chamber. When the transfer chamber is connected to the loadlock chamber, a pressure of the transfer chamber may be changed into a pressure of the loadlock chamber. When the transfer chamber is connected to the test chamber, the pressure of the transfer chamber may be changed into a pressure of the test chamber.
MODULAR AND ADJUSTABLE THERMAL LOAD TEST VEHICLE
A device for simulating thermal loads includes a platform and a plurality of nodes supported by the platform. At least one node is a movable node connected to the platform by a movable stage to move the movable node relative to the platform.
HIGH CURRENT DEVICE TESTING APPARATUS AND SYSTEMS
Embodiments of the present invention provide systems and methods for performing automated device testing at high power using ATI-based thermal management that substantially mitigates or prevents the pads and pins thereof from being burned or damaged. In this way, the lifespan of the testing equipment is improved and the expected downtime of testing equipment is substantially reduced, while also reducing cost of operation.
Planar ring radiation barrier for cryogenic wafer test system
One example includes a cryogenic wafer test system. The system includes a first chamber that is cooled to a cryogenic temperature and a wafer chuck confined within the first chamber. The wafer chuck can be configured to accommodate a wafer device-under-test (DUT) comprising a plurality of superconducting die. The system also includes a second chamber that is held at a non-cryogenic temperature and which comprises a wafer chuck actuator system configured to provide at least one of translational and rotational motion of the wafer chuck via mechanical linkage interconnecting the wafer chuck and the wafer chuck actuator system. The system further includes a radiation barrier arranged between the first chamber and the second chamber and through which the mechanical linkage extends, the radiation barrier being configured to provide a thermal gradient between the cryogenic temperature of the first chamber and the non-cryogenic temperature of the second chamber.
Test handler and semiconductor device equipment including same
A test handler includes a pusher which includes a pusher end which comes into contact with a DUT (Device Under Test) to transfer heat, and a pusher body which conducts heat to the pusher end, the pusher end separating a test tray for fixing the DUT and the pusher body from each other; a porous match plate including a pusher arrangement region in which the pusher body is placed, and a plurality of holes placed adjacent to the pusher arrangement region; a heater placed on an upper surface of the porous match plate to control temperature of the pusher; and an airflow input port placed on the heater to provide the airflow to the plurality of holes, in which the airflow passes through the plurality of holes and passes through a separated space between the test tray and the pusher body.
Reconfigurable LED load board clamp
A reconfigurable load board clamp is disclosed. The reconfigurable load board clamp includes first and second slotted ends; first and second opposing sides laterally coupled to the first and second slotted ends; and a MCPCB pin board removably coupled to the first and second slotted ends. The pin board includes a card edge connector plugged into an end of the pin board and multiple spring-loaded pin connectors. In implementations, multiple pin boards may be removed and added to the reconfigurable load board clamp to form a pin array suitable for a particular load board.
INTEGRATED CIRCUIT CHIP HAVING BACK-SURFACE TOPOGRAPHY FOR ENHANCED COOLING DURING CHIP TESTING
Embodiments of the invention include a method of preparing an integrated circuit (IC) chip to participate in test operations. The method includes accessing a back surface of the IC chip and adding a back-surface topography to the back surface. A surface area of the back-surface topography is greater than a surface area of the back surface.