A semiconductor storage device, an operating method thereof, and an analysis system capable of analyzing a defect during a specific operation is provided. A semiconductor chip provided by the disclosure determines that whether the semiconductor storage device is in a power-on mode based on a voltage supplied to an external terminal and executes a power-on sequence when the semiconductor storage device is in the power-on mode. The semiconductor chip then determines that whether execution of a break sequence is set, and if the execution is set, the semiconductor chip executes the break sequence. In the break sequence, a selected operation is executed, so that an operation being executed is stopped at a selected timing. A defect of the semiconductor chip is analyzed in a stopped state.

Systems and methods are provided for an automated analog fault injection including creating a list of fault models for injection to an analog circuit, adding a first fault placeholder to the analog circuit, running fault simulations by replacing the first fault placeholder with a first fault model from the list of fault models, and determining whether the first fault model is detected.

A method for defect identification for an integrated circuit includes determining a defect ranking technique, applying at least two defect identification techniques and generating a defect report corresponding to each technique, comparing the defect reports and generating probable defect locations, prioritizing the probable defect locations according to the defect ranking technique; and generating a report of the prioritized probable defect locations.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a touchless testing platform employed to, for example, create automated testing scripts, sequence test cases, and implement determine defect solutions. In one aspect, a method includes the actions of receiving requirements documentation for an application through a user interface (UI), analyzing the requirements documentation to extract terminologies based on an entity term corpus; categorizing the extracted terminologies based on a corpus of known terms; generating a semantic graph from standardized statements constructed from the categorized extracted terminologies; generating a process flow map for the application by identifying processes of the application and a respective relationship between each process from the semantic graph; generating a test scenario map of test scenarios for the application from the process flow map and the semantic graph; and providing the test scenario map to a tester through the UI.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a touchless testing platform employed to, for example, create automated testing scripts, sequence test cases, and implement determine defect solutions. In one aspect, a method includes the actions of receiving a log file that includes log records generated from a code base; processing the log file through a pattern mining algorithm to determine a usage pattern; generating a graphical representation based on an analysis of the usage pattern; processing the graphical representation through a machine learning algorithm to select a set of test cases from a plurality of test cases for the code base and to assign a priority value to each of the selected test cases; sequencing the set of test cases based on the priority values; and transmitting the sequenced set of test cases to a test execution engine.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a touchless testing platform employed to, for example, create automated testing scripts, sequence test cases, and implement defect solutions. In one aspect, a method includes receiving a log file and testing results generated from a code base for an application; processing the log file through a pattern-mining algorithm to determine a usage pattern of code modules within the code base; clustering defects from the testing results based on a respective functionality of the application reported within each of the defects; generating testing prioritizations for test cases for the application by assigning weightages to the test cases based on the clusters of defects and the usage pattern of the code modules within the code base; sequencing a set of the test cases based on the test prioritizations; and transmitting the sequence to a test execution engine.

Examples of techniques for modifying testing tools are described herein. An example computer-implemented method includes receiving, via a processor, a netlist comprising a complex coverage event that depends on a singular independent signal. The method includes detecting, via the processor, that complex coverage event can be separated into the singular independent signal and a logic state based on a structural logic analysis. The method also includes modifying, via the processor, a testing tool to test the netlist based on the singular independent signal.

A method is provided for testing the functionality of a device under test interface circuitry located between automated testing equipment (ATE) and a device under test (DUT). The method includes disconnecting the device under test from the device under test interface circuitry, utilizing a Source Measurement Unit (SMU) that generates and measures voltage and current and uses force and sense lines, and testing a switch located in the device under test interface circuitry using a two-state alarm process. The method also includes applying a voltage using the a voltage source measurement device in a first state in which force and sense lines of the voltage source measurement device are connected in the device under test interface circuitry. The method further includes detecting whether an alarm signal due to an open circuit has been activated, and determining that the switch being tested in the device under test interface circuitry is operating properly by the absence of the alarm signal being activated.

Techniques relate to an interactive logic diagnostic process. A diagnostic iteration loop is performed. When a critical failure does not have the diagnostic resolution that meets a predefined diagnostic resolution, potential faults related to the critical failure are isolated. When the critical failure has a diagnostic resolution that meets the predefined diagnostic resolution, the diagnostic iteration loop ends. Path focused fault test patterns are applied to the device under test in order to generate updated results of the path focused fault test patterns, such that the diagnostic resolution has been increased because a number of the potential faults related to the critical failure has decreased, and/or a size of a physical area of the potential faults related to the critical failure has decreased. The diagnostic iteration loop is returned to.

Systems and methods are provided for automated analog fault injection including creating a list of fault models for injection to an analog circuit, adding a first fault placeholder to the analog circuit, running fault simulations by replacing the first fault placeholder with a first fault model from the list of fault models, and determining whether the first fault model is detected.