The operational mode information and the hold-toggle pattern for a flexible isometric test compression system may be determined based on the plurality of test cubes generated for a subset of the targeted faults, the predetermined size and toggle rate for the hold-toggle pattern, and the predetermined maximum number of device inputs for full-toggle scan chains. The operational mode information comprising information of the full-toggle scan chains may be determined based on reduced toggle ranges first and the hold-toggle pattern may then be determined using a relaxation method. Alternatively, the hold-toggle pattern and the full-toggle scan chains may be determined incrementally together.

A system and method for providing convergence centric coverage for clock domain crossing (CDC) jitter in simulation is described. The method includes, in part, defining one or more design constraints associated with the circuit design, determining at least one group of converging signals associated with the circuit design using the one or more design constraints, applying a multitude of jitters to clock domain crossing (CDC) paths of the at least one group of converging signals, and storing the jitters in a jitter database.

An integrated circuit (IC) test engine extracts an input to output propagation delay for each cell instance of each of a plurality of cell types in an IC design from an SDF file for the IC design. The IC test engine extracts a node slack of each cell instance of each of the plurality of cell types of the IC design from a node slack report. The IC test engine also generates cell-aware test patterns for each cell instance of each cell type in the IC design to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of a plurality of candidate defects characterized in the plurality of fault rules files. Each cell-aware test pattern is configured to sensitize and propagate a transition along the longest possible path to test small delay defects in cell instances of the fabricated IC chip.

A fault rules engine generates a plurality of fault rules files, each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design. Each fault rules file includes data quantifying a nominal delay for a given two-cycle test pattern and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects of a given cell type of the plurality of cell types in the IC design. An IC test engine extracts an input to output propagation delay for each cell instance from a standard delay format (SDF) file for the IC design and generates cell-aware test patterns for each cell instance of each cell type in the IC design based on the plurality of fault rules files and the extracted input to output propagation delays.

A test and measurement system includes a primary instrument having an input for receiving a test signal for measurement or analysis from a Device Under Test (DUT) and generating a test waveform from the test signal, and a duplicator for sending a copy of the test waveform to one or more secondary instruments. The one or more secondary instruments are each structured to access the copy of the test signal for analysis, and each of the one or more secondary instruments includes a receiver structured to receive a command related to measurement or analysis of the copy of the test waveform, one or more processes for executing the received command, and an output for sending results of the executed command to be displayed on a user interface that is separate from any user interface of the one or more secondary instruments.

A circuit debug apparatus for debugging an integrated circuit that causes a functional fault may include a processor configured to extract a scan pattern of a scan chain of the integrated circuit while the integrated circuit is in a scan mode. The scan pattern includes a plurality of logic states for a corresponding plurality of logic circuits of the integrated circuit. The processor may also be configured to apply a modified scan pattern to the integrated circuit while the integrated circuit is in the scan mode, where the modified scan pattern includes a test pattern configured to eliminate the functional fault. The processor may be further configured to determine whether the integrated circuit with the modified scan pattern produces the functional fault while the integrated circuit is in a functional mode.

Techniques are disclosed for combining diagnostic features at different levels (with a special consideration of the application-oriented measures) though a quantitative analysis that provides evidence supporting a claimed diagnostic coverage (DC) calculation for circuits to meet defined functional safety standards. These techniques implement a parametrized approach to allow tuning by a system integrator according to its specific software application environment. The required safety level or DC goals may thus be attained based upon the results of the safety analysis (and failure rates) provided by a device manufacturer.

An integrated circuit (IC) design comprising a scan chain may be received, where stimulus values may be scanned-in and response values may be scanned-out through a scan path in the scan chain, where the scan path may include a first scan cell and a second scan cell such that the first scan cell is downstream with respect to the second scan cell. The scan chain may be modified to enable observation of a 0 and a 1 value in the first scan cell in presence of a defect in the second scan cell, or observation of a 0 and a 1 value in the second scan cell in presence of a defect in the first scan cell.

The computer-implemented method for testing a technical system having a plurality of technical components includes: providing a safety model modeling a safety relevant functionality of the technical system, providing a test model including test cases for testing the technical system, linking elements of the safety model with elements of the test model for enabling a tracing between the test cases of the test model and the safety-relevant functionality of the safety model, generating test parameters for at least one certain test case of the test cases and/or a new test case for the test model using the safety model linked to the test model, and testing the technical system using the certain test case and/or the new test case. Further, a computer program product, a computerized device and an arrangement having a technical system and a computerized device are provided.

The computer-implemented method for testing a technical system having a plurality of technical components includes: providing a safety model modeling a safety relevant functionality of the technical system, providing a test model describing test cases for testing the technical system, linking elements of the safety model with elements of the test model for enabling a tracing between the test cases of the test model and the safety-relevant functionality of the safety model, testing the technical system using at least one of the test cases generated based on the test model linked with the safety model, and analyzing the testing for providing coverage criteria for the safety-relevant functionality. Further, a computer program product, a computerized device and an arrangement having a technical system and a computerized device are suggested.