The system and method of using a debug interface recorder and replay unit for debugging and testing devices of interest such as integrated circuits by using a debug interface buffer controller to receive, record, and replay sequences of instructions to the integrated circuit. This is particularly useful for deployed devices that are difficult or dangerous to access. This is also beneficial for devices that cannot be reached (e.g., after launch). By recording sequences and storing them for later use, and by communicating commands and configuration settings to a device, system maintenance and troubleshooting is accomplished saving valuable time and money without requiring physical access to the device of interest.

An example system includes a processor to receive a template-aware coverage data that tracks probabilities of events in a list of events being hit for a set of test-templates over a first and second predetermined period of time. The processor is to generate a hit prediction score for each combination of unhit event in the events and each test-template in the set of test-templates of the second predetermined period of time. The hit prediction score indicates a probability of an unhit event being hit by a particular test-template in a future third predetermined period of time based on the template-aware coverage data and similarities between the events and the test-templates. The processor is to generate a template score for each test-template based on the hit prediction scores for each test-template. The processor is to select a test-template from the set of test-templates based on the template score.

A first score and a second score for each scan cell are first determined based on numbers of test cubes in a set of test cubes having a specified value of 1 and a specified value of 0 for the each scan cell, respectively. A ranking score for each test cube in the set of test cubes is then determined based on combining the first scores and the second scores corresponding to specified bits of the each test cube in the set of test cubes. Test cubes in the set of test cubes are merged according to a sequence based on the ranking scores in a test pattern generation process.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a touchless testing platform employed to, for example, create automated testing scripts, sequence test cases, and implement determine defect solutions. In one aspect, a method includes the actions of receiving a log file that includes log records generated from a code base; processing the log file through a pattern mining algorithm to determine a usage pattern; generating a graphical representation based on an analysis of the usage pattern; processing the graphical representation through a machine learning algorithm to select a set of test cases from a plurality of test cases for the code base and to assign a priority value to each of the selected test cases; sequencing the set of test cases based on the priority values; and transmitting the sequenced set of test cases to a test execution engine.

Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for in-field safety tests on system-level and circuit-level, providing real-time and on-chip tests with respect to, including but not limited to, circuit reliability, power consumption, and system safety. The in-field safety tests may include implementing voltage droop monitors (VDMs) and signature collectors with authentication-enabled launching. Other embodiments may be described and claimed.

A system and method for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a touchless testing platform employed to, for example, create automated testing scripts, sequence test cases, and implement defect solutions. In one aspect, a method includes receiving a log file and testing results generated from a code base for an application; processing the log file through a pattern-mining algorithm to determine a usage pattern of code modules within the code base; clustering defects from the testing results based on a respective functionality of the application reported within each of the defects; generating testing prioritizations for test cases for the application by assigning weightages to the test cases based on the clusters of defects and the usage pattern of the code modules within the code base; sequencing a set of the test cases based on the test prioritizations; and transmitting the sequence to a test execution engine.

A semiconductor storage device, an operating method thereof, and an analysis system capable of analyzing a defect during a specific operation is provided. A semiconductor chip provided by the disclosure determines that whether the semiconductor storage device is in a power-on mode based on a voltage supplied to an external terminal and executes a power-on sequence when the semiconductor storage device is in the power-on mode. The semiconductor chip then determines that whether execution of a break sequence is set, and if the execution is set, the semiconductor chip executes the break sequence. In the break sequence, a selected operation is executed, so that an operation being executed is stopped at a selected timing. A defect of the semiconductor chip is analyzed in a stopped state.

Examples of techniques for modifying testing tools are described herein. An example computer-implemented method includes receiving, via a processor, a netlist comprising a complex coverage event that depends on a singular independent signal. The method includes detecting, via the processor, that complex coverage event can be separated into the singular independent signal and a logic state based on a structural logic analysis. The method also includes modifying, via the processor, a testing tool to test the netlist based on the singular independent signal.

A mixed signal testing system capable of testing differently configured units under test (UUT) includes a controller, a test station and an interface system that support multiple UUTs. The test station includes independent sets of channels configured to send signals to and receive signals from each UUT being tested and signal processing subsystems that direct stimulus signals to a respective set of channels and receive signals in response thereto. The signal processing subsystems enable simultaneous and independent directing of stimulus signals through the sets of channels to each UUT and reception of signals from each UUT in response to the stimulus signals. Received signals responsive to stimulus signals provided to a fully functional UUT (with and without induced faults) are used to assess presence or absence of faults in the UUT being tested which may be determined to include one or more faults or be fault-free, i.e., fully functional.