A semiconductor device includes chips, wherein a first chip: an internal circuit; first selectors to output signals from one of first outputs; second selectors to output signals from one of second outputs; first output buffer units to relay/interrupt signals output from one of the first outputs; second output buffer units to relay/interrupt signals output from one of the second outputs; first terminals to output a signal from the respective first output buffer units and belong to a first group in which the first terminals are placed at positions distant by first distances; and second terminals to output a signal from the respective second output buffer units and belong to a second group in which the second terminals are placed at positions distant by second distances and each of the second terminals is placed at a position distant from an adjacent first terminal of the first terminals by third distances.

This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

A stack type semiconductor apparatus may be provided. The stack type semiconductor apparatus may include a plurality of semiconductor chips stacked and configured for transferring signals through through-hole vias. Each of the plurality of stacked semiconductor chips may include an error detection circuit configured to perform a down scan for transferring a signal to a lower direction and an up scan for transferring a signal to an upper direction through through-hole vias in a column direction among the through-hole vias, and to determine whether the through-hole vias have failed according to a down scan result value and an up scan result value.

The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly to structures and methods of directly testing semiconductor wafers having micro-solder connections. According to one embodiment of the present invention, a method of forming a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer, is disclosed. According to another embodiment, a method of testing the pattern of micro-solder connections is disclosed. According to another embodiment, a novel electrical probe tip structure, having contacts on the same pitch as the pattern of micro-solder connections is disclosed.

Systems and methods are provided for an integrated circuit system. A plurality of separate integrated circuit dies are coupled together to form an integrated circuit package, a first integrated circuit die including an input and a last integrated circuit die including an output, ones of the plurality of integrated circuit dies including a testing circuit associated with a corresponding integrated circuit die. The testing circuit includes a testing path for testing functionality of the corresponding integrated circuit die, a bypass path bypassing the testing path, and control circuitry for selecting between an output of the testing path and an output of the bypass path, the control circuitry being configured to select the output of the testing path or the output of the bypass path and to pass the selected output to a subsequent integrated circuit die among the plurality of coupled circuit dies.

Aspects of the invention relate to scan-based test architecture for interconnects in stacked designs. The disclosed scan-based test architecture comprises a scan chain. Scan cells on the scan chain are configured to receive data from, based on bits of a control signal, outputs of neighboring scan cells or outputs of mixing devices that combine data from through-silicon vias with data from the outputs of the neighboring scan cells. The scan-based test architecture can be used to identify single or multiple defective through-silicon vias.

Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.

A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.

An electronic assembly has a host wafer having a first circuit including wafer transistors and passive, non-transistor devices. Chiplets have a second circuit including at least one radio frequency (RF) transistor device. Electrical interconnects are between the chiplets and wafer. The electrical interconnects electrically connect the first circuit to the second circuits. Oscillators that have the wafer transistor, the RF transistor and the electrical interconnects produce a signal for built-in self-test circuits for testing an assembly design of the electronic assembly and speeds of the RF chiplet transistors.