An integrated circuit comprising a field programmable gate array including a plurality of logic tiles, wherein, during operation, each logic tile is configurable to connect with at least one other logic tile, and wherein each logic tile includes: (1) a normal operating mode and test mode, (2) an interconnect network including a plurality of multiplexers, wherein during operation, the interconnect network of each logic tile is configurable to connect with the interconnect network of at least one other logic tile in the normal operating mode and (3) bitcells to store data. The FPGA also includes control circuitry, electrically connected to each logic tile, to configure each logic tile in a test mode and enable concurrently writing configuration test data into each logic tile of the plurality of logic tiles when the FPGA is in the test mode.

Aspects of the invention include systems and methods directed to a portable chip tester. A non-limiting example of a system includes a housing, a printed circuit board mounted on the housing, in which the printed circuit board includes a first interface operable to permit electrical communication between the printed circuit board and a device under test. The system further includes a mount operable to enable an electrical connection with an integrated circuit, in which the integrated circuit is operable to manage testing the device under test under a testing protocol. The system further includes a power supply and a software platform that includes a memory having computer readable instructions and one or more processors for executing the computer readable instructions. The computer readable instructions controlling the processors to perform operations including directing the integrated circuit to manage testing of the device under test pursuant to the testing protocol.

A programmable semiconductor device contains a wireless communication block (WCB) capable of facilitating wirelessly field programmable gate array (FPGA) programming download as well as functional logic implementation. In one aspect, WCB detects an FPGA access request for initiating an FPGA reconfiguration from a remote system via a wireless communications network. Upon receiving a configuration bitstream for programming the FPGA via the wireless communications network, the configuration bitstream is forwarded from WCB to a configuration download block (CDB) for initiating a configuration process. CDB subsequently programs at least a portion of configurable logic blocks (LBs) in FPGA in response to the configuration bitstream.

In an approach, a processor receives an input indicative of a set of registers, the set of registers being configured for obtaining output data from a design-under-test (DUT) in a field-programmable gate array (FPGA) module. A processor executes a set of instructions for monitoring the output data in the set of registers;. A processor generates data indicative of at least one portion of changes of the output data in the set of registers during the execution of the set of instructions. A processor causes a separate machine to analyze the data via utilizing an interface to send the data to the separate machine.

A programmable semiconductor device contains a wireless communication block (WCB) capable of facilitating wirelessly field programmable gate array (FPGA) programming download as well as functional logic implementation. In one aspect, WCB detects an FPGA access request for initiating an FPGA reconfiguration from a remote system via a wireless communications network. Upon receiving a configuration bitstream for programming the FPGA via the wireless communications network, the configuration bitstream is forwarded from WCB to a configuration download block (CDB) for initiating a configuration process. CDB subsequently programs at least a portion of configurable logic blocks (LBs) in FPGA in response to the configuration bitstream.

An emulation system may include an emulator. The emulator may include at least one chip and at least one FPGA. The chip may be associated with the FPGA. The FPGA may operate as a coprocessor to implement in-system scan test of the chip. In a scan mode of the in-system scan test, the coprocessor may transmit one or more in-system test instructions to the chip through its existing connections with the chip. The coprocessor may capture test response data from the chip in response to the one or more in-system test instructions through its existing connections with the chip. In an offline mode, the coprocessor may compare the test response data with expected response data to determine if the chips are functioning correctly.

A server switch system includes a switch unit and a field-programmable gate array (FPGA) unit. The switch unit includes a first switch interface for receiving the first data and sending the second data, and a second switch interface for sending the third data and receiving the fourth data. The switch unit is used to generate the third data according to the first data, and generate the second data according to the fourth data. The FPGA unit includes an FPGA interface coupled to the second switch interface for receiving the third data from the switch unit and sending the fourth data to the switch unit.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a test system configuration adapter includes a tester side socket, a break out pin, and a device under test (DUT) side slot. The tester side socket is configured to couple with a test equipment socket. The break out pin is configured to couple with the supplemental equipment. The DUT side slot is configured to couple with the tester side socket, the break out pin, and a DUT. The test system configuration adapter is configured to enable communication between test equipment coupled to the test equipment socket and supplemental equipment coupled to the breakout pin while the DUT remains coupled to the DUT side slot. The breakout pin and tester side socket can be selectively coupled to the DUT side slot.

An integrated circuit is described. The integrated circuit comprises an analog-to-digital converter circuit configured to receive an input signal at an input and generate an output signal at an output; and a monitor circuit coupled to the output of the analog-to-digital converter circuit, the monitor circuit configured to receive the output signal and to generate integration coefficients for the analog-to-digital converter circuit; wherein the integration coefficients are dynamically generated based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.

A method for testing autonomous reconfiguration logic for an electromechanical actuator includes executing a plurality of test cases against a computer model configured and operable to implement autonomous reconfiguration logic for an electromechanical actuator including a plurality of electromechanical motors to generate a first set of test results. The method further includes executing the plurality of test cases against a programmable logic device configured and operable to implement the autonomous reconfiguration logic for the electromechanical actuator to generate a second set of test results and comparing the first set of test results to the second set of test results.