Methods and systems for determining a systematic defect in a circuit under test is provided. Elements of the circuit under test converted into scan cells. A first scan chain that includes a first plurality of scan cells is formed. Each scan cell of the first plurality of scan cells of the first scan chain are of a first cell type. The first scan chain contains a first scan input and a first scan output. A first test pattern is applied at the scan input and a first test output is collected for the applied first test pattern at the first scan output. The collected first test output is compared with a first expected test output. The first cell type is marked to be a suspect for a systematic defect when the first test output is different from the first expected test output.

A method of testing a device under test, the device under test comprising a scan chain having a number of storage elements. The method determines a representation of toggling events in a test sequence, where the test sequence is for testing the scan chain. The method also selectively times input of a bit sequence, corresponding to the test sequence, to a first storage element in the number of storage elements, and through the scan chain, in response to the determining step.

Testing systems and method of testing an integrated circuit are provided. A testing system comprises an input terminal, multiple circuit elements, each having a register, and an output terminal forming a scan chain through which an input signal is propagated. The testing system further comprises a debugger that includes a mapping module that stores information mapping register values to their respective functional meanings. The input signal is applied to extract all values of all of the registers whether or not accessible by a processor.

A test circuit includes flip-flops operating in synchronization with a clock signal, a timing adjustment circuit to generate a first set signal that provides a command that sets output signals from the flip-flops at a predetermined logic, and a second set signal that provides a command that detects a fault in the output signals from the flip-flops, and to set timing for cancellation of the command of the second set signal, the timing being delayed by n cycles of the clock signal from timing for cancellation of the command of the first set signal, and a fault detection circuit to output a fault detection signal during a period of time from the cancellation of the command of the first set signal to the cancellation of the command of the second set signal, if there is an output signal having a different logic in the output signals from the flip-flops.

An apparatus that allows for access to any and all registers of a central processing unit in a line replaceable unit (LRU) without a need to open the housing of the LRU is provided. The apparatus may receive write or read packets from an external device and relay the same to an LRU. The apparatus may receive state information from one or more registers of the LRU in response. The apparatus may transmit or transfer the state information to an external device. The apparatus may be used to update firmware in the LRU, for diagnostics or testing.

A processing device (30, 710) for reducing scan traffic is provided. The processing device (30, 710) comprises one or more interfaces (32, 718) configured to transmit information to at least one register access interface (759, 761) and processing circuitry (34) configured to control the one or more interfaces. Further, the processing circuitry (34) is configured to obtain register parameters of at least one functional unit (760, 762) of a processing unit (750) and to generate an improved bulk register comprising the register parameters of the at least one functional unit.

Methods and systems for determining a systematic defect in a circuit under test is provided. Elements of the circuit under test converted into scan cells. A first scan chain that includes a first plurality of scan cells is formed. Each scan cell of the first plurality of scan cells of the first scan chain are of a first cell type. The first scan chain contains a first scan input and a first scan output. A first test pattern is applied at the scan input and a first test output is collected for the applied first test pattern at the first scan output. The collected first test output is compared with a first expected test output. The first cell type is marked to be a suspect for a systematic defect when the first test output is different from the first expected test output.

A method and circuit for implementing register array repair using Logic Built In Self Test (LBIST), and a design structure on which the subject circuit resides are provided. Register array repair includes identifying and creating a list of any repairable Register Arrays (RAs) that effect an LBIST fail result. Next a repair solution is detected for each of the repairable Register Arrays (RAs) isolating a failing location for the detected repair solution for each array.

A method for testing a chip comprising receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.

Systems, methods, and circuitry are provided for a sorting array. In one example, a sorting array element includes an output register and control circuitry. The output register is configured to store an output value. In response to a cell under test (CUT) load signal the output register stores a CUT value and in response to a first register shift signal from a previous sorting array element the output register stores contents of an output register of the previous sorting array element. The control circuitry is configured to generate the CUT load signal and a second register shift signal for a subsequent sorting array element based on relative magnitudes of the CUT value, the output value, and an output value stored in the output register of the previous sorting array element.