An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between the top surface and the bottom surface. A through silicon via (TSV) has a conductive body in the opening, has a top contact point coupled to the body at the top surface, and has a bottom contact point coupled to the body at the bottom surface. A scan cell has a serial input, a serial output, control inputs, a voltage reference input, a response input coupled to one of the contact points, and a stimulus output coupled to the other one of the contact points.

The present application provides a circuit and an associated chip. The circuit is coupled to a memory. The circuit includes: a first scan flip-flop (FF), being a previous-stage scan FF of an input terminal of the memory and having an output terminal coupled to an input terminal of the memory; and a second scan FF, being a next-stage scan FF of an output terminal of the memory and having an input terminal coupled to an output terminal of the memory; wherein a scan mode of the circuit has a load phase and a capture phase, during the capture phase, data output from the output terminal of the first scan FF loops back to a data input terminal of the first scan FF via a first loop, and the first loop is free from passing through the second scan FF.

A vertical field effect transistor (VFET) cell implementing a VFET circuit over a plurality of gate grids includes: a 1.sup.st circuit including at least one VFET and provided over at least one gate grid; and a 2.sup.nd circuit including at least one VFET and provided over at least one gate grid formed on a left or right side of the 1.sup.st circuit, wherein a gate of the VFET of the 1.sup.st circuit is configured to share a gate signal or a source/drain signal of the VFET of the 2.sup.nd circuit, and the 1.sup.st circuit is an (X−1)-contacted poly pitch (CPP) circuit, which is (X−1) CPP wide, converted from an X-CPP circuit which is X CPP wide and performs a same logic function as the (X−1)-CPP circuit, X being an integer greater than 1.

A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.

A register circuit for which an initial value can be changed without using a flip-flop including both a set terminal and a reset terminal is provided. The register circuit includes an initial value wiring line, a write signal terminal, a clock signal terminal, a first flip-flop, an output control circuit, a second flip-flop, and a selector.

According to one embodiment, a semiconductor device includes: a first scan chain and a second scan chain each including a plurality of cascaded flip-flops; a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction; and a clock control circuit that supplies a first clock to the first scan chain and a second clock to the second scan chain, the second clock having timing different to that of the first clock. The plurality of flip-flops are arranged along the second direction.

A bi-directional scan chain includes a plurality of cell structures, each cell structure having a storage device and at least one multiplexer, the plurality of cell structures coupled to one another in a series configuration, wherein an output of a (K-1)-th cell structure is provided as input to the K-th cell structure to provide a forward data shifting operation, and an output of the K-th cell structure is provided as an input to the (K-1)-th cell structure to provide a backward data shifting operation, where K is an integer greater than 1.

A circuit for implementing a scan chain in an integrated circuit having a clock domain crossing is described. The circuit comprises a first dual-edge storage circuit configured to receive an input signal at a scan input and to receive a first clock signal in a first clock domain at a clock input; a storage element having a data input configured to receive an output of the first dual-edge storage circuit; a second dual-edge storage circuit configured to receive an output of the storage element at a scan input and to receive a second clock signal in a second clock domain at a clock input; and a pulse generator configured to provide, to a clock input of the storage element, a pulse signal having a pulse width selected to enable the second dual-edge storage element to store the output of the first dual-edge storage element.

A circuit includes a plurality of scan chains arranged in a ring network topology. Each scan chain includes a plurality of scan blocks, each of the plurality of scan blocks including a storage element and a switching device. Each switching device includes a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed, and a second input configured to receive one of a function logic signal or a test scan signal. The switching device configured to selectively couple the first input or the second input to an input of the storage element.

Multi-bit data flip-flops are disclosed that provide bit initialization through propagation of scan bits. Input multiplexers are configured to select between input data bits and input scan bits based upon mode select signals. Master latches receive and latch outputs from the input multiplexers. Slave latches receive and latch outputs from the master latches and also provide propagated input scan bits to the input multiplexers. A first state for the mode select signals selects the input data bits for a data mode of operation, and a second state for the mode select signals selects the input scan bits for a scan mode of operation. Further, the input multiplexers, master latches, and slave latches are configured to operate in an initialization mode to pass a fixed input scan bit through the multi-bit data flip-flop based upon initialization signals (e.g., set and/or reset signals).