An integrated circuit (IC) includes subcircuits, power switches coupled to pass load current to a respective one of the subcircuits when activated by a respective switch control signal, and sensing circuits. Each of the sensing circuits is coupled to a respective one of the subcircuits, wherein the sensing circuits are configured to generate sense currents that are proportional to the respective load currents. The IC also includes a conversion circuit configured to receive at least one of the sense currents and to convert the at least one of the sense currents to an equivalent multi-bit digital signal, a timestamp circuit configured to generate a timestamp value that is correlated with the multi-bit digital signal, and a controller configured to provide signals to operate the power switches and the sensing circuits.

Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.

A circuit includes: a first power domain including: an isolation cell, a first selection circuit having inputs for receiving a first functional signal and a first test signal and an output for controlling the isolation cell, and a second selection circuit having inputs for receiving a second functional signal and a second test signal and an output coupled to a signal input of the isolation cell; a second power domain including: a first circuit having an input coupled to a signal output of the isolation cell, a first observation element coupled to the signal output of the isolation cell, and a second observation element coupled to an output of the first circuit; where, when in test mode, the first selection circuit controls the isolation cell based on the first test signal, and the second selection circuit provides the second test signal to the signal input of the isolation cell.

A semiconductor device comprises a central processing device, a first logical circuit, and a serial memory interface circuit. The first logical circuit has a first scan chain in which a first scan pattern is set, is configured to suppress a leakage current when the first scan pattern for power saving is set in the first scan chain. The serial memory interface circuit is configured to acquire the first scan pattern for power saving from an external storage device. The leakage current of the first logical circuit is suppressed by transferring the first scan pattern for power saving acquired by the serial memory interface circuit to the first logical circuit and setting the first scan pattern for power saving in the first scan chain under control of the central processing device.

Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

A power consumption measurement assembly includes: at least two sampling modules respectively connected to a circuit to be measured in series; a gating module configured to gate one of the at least two sampling modules; an amplifying module configured to acquire and amplify a voltage signal across the gated sampling module; and a processing module connected to the gating module and the amplifying module and configured to: control and adjust the gated sampling module and an amplification of the amplifying module, calculate a power consumption value based on the amplified voltage signal and transmit the power consumption value.

An extended joint test action group based controller and a method of use allows easier testing of integrated circuits by reducing the power dissipation of an IC. The extended joint test action group (JTAG) controller tests internal storage elements that form digital units in an integrated circuit (IC) use a design for testing scan infrastructure on the IC, wherein the JTAG controller is extended by an overall reset generator for all digital units of the IC, and a finite state machine controls the overall reset generator. In reset mode the JTAG controller stops the at least one clock module in supplying the digital units that should be reset. It then sets all scan chains in test mode and switches the input multiplexers into reset mode; and then controls the number of shift clock cycles for shifting in the reset value to the flip-flops in the scan chain, respectively.

A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.

A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.

Apparatuses of a scan controller include memory and circuitry, where the circuitry is configured to respond to a first signal by sending a second signal to isolate state retention elements from non-state retention elements in a scan chain of power gating circuitry and cycling through the scan chain while obtaining state retention data from the state retention elements during each cycle. The circuitry may be further configured to determine a first error detection code from the state retention data and store the error detection code in the memory. The circuitry may be configured to determine a second error detection code in response to another signal and compare the first error detection code with the second error detection code. The circuitry may be configured to send a signal indicating that the state retention data is corrupted if the first error detection code does not match the second error detection code.