A non-volatile computer data storage programming system includes a scan chain modification configured to receive a default model defining a scan chain of an industry standardized device. A controller is in signal communication with the scan chain modification system, and is configured to program an industry standardized device. A non-volatile computer data storage device is configured to receive data from the industry standardized device. The scan chain modification system modifies the default model to generate a new model including a reduced scan chain, and the controller programs the industry standardized device based on the new model such that the industry standardized device is programmed with the reduced scan chain.

This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.

A method and a memory device are provided. Data is obtained for a scan operation at an input buffer of a scan kernel in the memory device. The input buffer is adaptable to a first mode and a second mode of the scan kernel. Preprocessing of the data from the input buffer is performed to generate preprocessed data. A different type of preprocessing is performed for the first mode and the second mode. The preprocessed data is filtered to generate a filtered result. The filtered result is provided from the scan kernel to a controller of the memory device.

Embodiments of apparatuses and methods for in-field testing of an integrated circuit (IC) are disclosed. In an embodiment, an apparatus includes an IC having circuitry to operate in a structural test mode, the structural test mode including a memory built-in self-test (MBIST) mechanism and an automatic test pattern generation (ATPG) mechanism; a microcontroller to enable and control the structural test mode during in-field operation of the IC; and a programmable logic device to support the ATPG mechanism.

Methods, systems, and devices for memory health status reporting are described. A memory device may output to a host device a parameter value, which may be indicative of metric or condition related to the performance or reliability (e.g., a health status) of the memory device of the memory device. The host device may thereby determine that the memory device is degraded, possibly prior to device or system failure. Based on the parameter value, the host device may take preventative action, such as quarantining the memory device, deactivating the memory device, or swapping the memory device for another memory device.

A DDR5 SDRAM DIMM slot detection system and a method thereof are disclosed. A first detection board is serially connected to a second detection board, a JTAG controller converts a DIMM detection instruction, which is generated by a detection device, into a DIMM detection instruction in JTAG format; the DIMM detection instruction in JTAG format is provided to the first detection board or second detection board through the adapter circuit board, so as to detect DDR5 SDRAM DIMM slots of the circuit board under test, thereby achieving the technical effect of improving efficiency in detection for DDR5 SDRAM DIMM connection interface.

A controller for a memory component comprises a processing unit and at least one memory unit coupled to the processing unit, the memory unit comprising at least a first area for storing a user firmware and a second area for storing a controller firmware; the processing unit is configured to capture a memory address of a program instruction to be executed, compare the memory address with a reference value, and, based on that comparison, enable/restricting actions associated with the program instruction. A related memory component and related methods are also disclosed.

A DDR5 SDRAM DIMM slot detection system and a method thereof are disclosed. A first detection board is serially connected to a second detection board, a JTAG controller converts a DIMM detection instruction, which is generated by a detection device, into a DIMM detection instruction in JTAG format; the DIMM detection instruction in JTAG format is provided to the first detection board or second detection board through the adapter circuit board, so as to detect DDR5 SDRAM DIMM slots of the circuit board under test, thereby achieving the technical effect of improving efficiency in detection for DDR5 SDRAM DIMM connection interface.