A test system is provided. The system includes a first test apparatus and a second test apparatus. A device power supply of the first test apparatus (ATE) is electrically connected with a device under test (DUT) through a driving branch (F) and a detecting branch (S), the driving branch (F) being configured to provide an original driving current to the DUT b the device power supply during testing, and the detecting branch (S) being configured to detect an effective driving current reaching the DUT. The second test apparatus includes a first voltage drop branch, the first voltage drop branch is connected to the detecting branch (S), and a voltage drop detected by the driving branch (F) is used to determine an effectiveness of an electrical connection formed between the driving branch and the device under test, and an electrical connection formed between the detecting branch (S) and the DUT.

A testkey includes two switching circuits and two compensation circuits. The first switching circuit transmits a test signal to a first DUT when the first DUT is being tested and functions as high impedance when the first DUT is not being tested. The second switching circuit transmits the test signal to a second DUT when the second DUT is being tested and functions as high impedance when the second DUT is not being tested. When the first DUT is not being tested and the second DUT is being tested, the first compensation circuit provides first compensation current for reducing the leakage current of the first switching circuit. When the first DUT is being tested and the second DUT is not being tested, the second compensation circuit provides second compensation current for reducing the leakage current of the second switching circuit.

A wafer test system includes a probe apparatus, a data server, an automation subsystem, and a probe mark assessment subsystem. The probe apparatus includes a probe card, a tester, and a camera. The probe card includes probe pins for contacting test pads in the wafer, and the camera captures an image of the test pads. The automation subsystem obtains an image specification from the probe apparatus and triggers an automated assessment of a probe mark in the image of the test pads. The probe mark assessment subsystem performs the automated assessment of the probe mark in the image of the test pads. The probe mark assessment subsystem performs an image-processing operation to obtain a probe mark assessment result, and the automation subsystem stops the probe apparatus if the probe mark assessment result indicates a probe test failure.

The invention is an assembly for checking the functionality of a measuring object, that is a DUT, in a medical implant or at least one part of the medical implant. The assembly comprises a test signal generator, a test module that is connected to the test signal generator. The assembly has a first receiving structure with at least one contact electrode, into which an adapter rigidly connects to the DUT in a releasable manner which is inserted to form least one electrical contact. A control and analysis unit is connected to the test signal generator and to the test module in a wired or wireless manner.

There is provided an attenuation amount setting unit that sets, in a case where signals are simultaneously output from all output ports of a plurality of interface units at the same signal level, one of the plurality of interface units as the reference interface unit, and adds a difference between an attenuation amount of a second attenuator stored in a storage unit of the reference interface unit and an attenuation amount of another second attenuator stored in another storage unit of the other interface unit to an attenuation amount of each of a plurality of third attenuators of the other interface unit to correct the attenuation amount.

Embodiments described herein may be directed to receiving a plurality of data captured, respectively, by a plurality of test instruments coupled to a device under test, wherein a plurality of data elements within, respectively, the plurality of captured data are associated with a timestamp based upon a time a data element was captured. Embodiments may also analyze the received plurality of data captured, respectively, by the one or more test instruments, and graphically display at least a portion of the analyzed plurality of captured data to a user. Other embodiments may be identified herein.

A test system of embodiments electrically connects one or more first semiconductor chips formed on a first wafer and one or more second semiconductor chips formed on a second wafer to perform tests on the one or more first and second semiconductor chips. The test system includes a test device that supplies a test signal to each of the one or more first semiconductor chips, a first probe device including a first probe to be connected to a first internal pad of each of the one or more first semiconductor chips and a first communication circuit configured to transmit and receive a signal, and a second probe device including a second probe to be connected to a second internal pad of each of the one or more second semiconductor chips and a second communication circuit configured to transmit and receive the signal to and from the first communication circuit.

The disclosure describes an apparatus for testing a component, wherein the apparatus is configured to apply a magnetic field with a magnetic field orientation from a set of magnetic field orientations to the component. The apparatus is further configured to perform a test on the component in the presence of the respective magnetic fields with the respective magnetic field orientations from the set of magnetic field orientations to obtain an information characterizing an operation of the component. The apparatus is also configured to determine a test result based on the information characterizing the operation of the component in the presence of different magnetic fields with different magnetic field orientations from the set of magnetic field orientations. The disclosure also describes a method of testing and a computer-readable storage device for implementing the method and provides more efficiency in view of reliability and costs.

The present disclosure provides a test apparatus and a jumper thereof. The test apparatus includes a base board and the jumper. The base board has a first slot and a second slot. The first slot has a plurality of electrical contacts, and is configured to receive a plurality of pins of a device under test. The jumper is inserted into the second slot. The jumper includes a body and a plurality of first circuits. The first circuits are disposed on the body and electrically connect the electrical contacts of the first slot to a plurality of pins of a tester.

A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.