Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

The present disclosure provides a microwave system, including a chamber and a microwave process circuit. The microwave process circuit is coupled to the chamber, and configured to radiate a polarized source microwave, receive a first reflected microwave, and radiate a polarized first reflected microwave into the chamber so as to heat a device under test in the chamber. The microwave process circuit includes a power generator, a first energy feeder, and a second energy feeder. The power generator is configured to generate a source microwave according to a reference signal and a control signal. The first energy feeder is configured to polarized the source microwave to the polarized source microwave, and radiate the polarized microwave into the chamber. The second energy feeder is configured to polarized the first reflected microwave to the polarized first reflected microwave, and radiate the polarized first reflected microwave into the chamber.

A method for detecting error on an input/output (IO) pin of an integrated circuit includes using the input/output pin of the integrated circuit in a first mode by receiving or sending a first value as analog data or digital data. The input/output pin is toggled in a test mode after each instance of using the input/output pin in the first mode. The test mode includes providing a second value disparate from the first value during a set time after using the input/output pin in the first mode, receiving back during the set time a resulting value based on providing the second value, measuring the resulting value, and identifying an error on the input/output pin of the integrated circuit based on the measured resulting value.

A fast calibration method for slide-screw impedance tuners employs a new tuner control board and routine with independent direct triggering and data sampling by the VNA; a new vertical scaling algorithm bypasses the traditional iterative approach and uses numerical curve-fitting and ISO circle definition. Full tuner calibration executes without motor stopping, yielding time reduction typically by a factor of 8.

Introduced herein is a technique that reliably measures on-die noise of logic in a chip. The introduced technique places a noise measurement system in partitions of the chip that are expected to cause the most noise. The introduced technique utilizes a continuous free-running clock that feeds functional frequency to the noise measurement circuit throughout the noise measurement scan test. This allows the noise measurement circuit to measure the voltage noise of the logic during a shift phase, which was not possible in the conventional noise measurement method. Also, by being able to measure the voltage noise during a shift phase and hence in both phases of the scan test, the introduced technique can perform a more comprehensive noise measurement not only during ATE testing but as part of IST in the field.

A circuit and a method for reducing interference of power on/off to hardware test. The circuit includes: a power unit, a voltage processing unit, a PSU and a to-be-tested hardware. An input terminal of the voltage processing unit is connected to the power unit, an output terminal of the voltage processing unit is connected to an input terminal of the PSU, and an output terminal of the PSU is connected to the to-be-tested hardware; the power unit is configured to provide an operating voltage; the voltage processing unit is configured to eliminate electric sparks caused by instability of the operating voltage at an instant of power on/off; the PSU is configured to convert a stable operating voltage outputted from the voltage processing unit into a direct current voltage required for the to-be-tested hardware; and the to-be-tested hardware is configured to receive the direct current voltage outputted from the PSU.

In a measurement system, a signal probing circuit may provide probed signals by probing voltages and currents and/or incident and reflected waves at a port of a device under test (DUT). A multi-channel receiver structure may include receivers that receive two probed signals from the signal probing hardware circuit, each receiver having its own sample clock derived from a master clock and further having a respective digitizer for digitizing a corresponding one of the two probed signals. A synchronization block, external to the receivers and including a reference clock derived from the master clock, may enable the two probed signals to be phase coherently digitized across the receivers by synchronizing the respective sample clocks of the receivers while the reference clock is being shared with the receivers. A signal processing circuit may then process the phase coherently digitized probed signals.

An apparatus that allows for access to any and all registers of a central processing unit in a line replaceable unit (LRU) without a need to open the housing of the LRU is provided. The apparatus may receive write or read packets from an external device and relay the same to an LRU. The apparatus may receive state information from one or more registers of the LRU in response. The apparatus may transmit or transfer the state information to an external device. The apparatus may be used to update firmware in the LRU, for diagnostics or testing.

The present invention relates to a self-diagnostic apparatus capable of improving safety of a device under test (DUT) by analyzing a characteristic change of a DUT, such as a semiconductor, a circuit module, or a system, in a safe operating region over time and allowing a regular test and a periodic test to be performed even while the DUT is running.

A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.