A virtualizable automated test equipment architecture includes a circuit assembly. The circuit assembly includes a number of signal paths that extend between a front plane and a backplane. The signal paths can be continuous and isolated from other signal paths of the plurality of signal paths. The circuit assembly also includes an impedance disposed along a signal path of the plurality of signal paths. A plurality of software-configurable physical disconnects may be arranged within the circuit assembly to form a switching matrix. The plurality of signal paths can be associated with a plurality of software-configurable physical disconnects, which can be configured to open and close signal paths of the plurality of signal paths based on the predetermined test requirements. The circuit assembly also includes a plurality of external device connections, at least one of which may be configured to interface with a unit under test (UUT). The software configurable physical disconnects may be configurable at runtime. Because the system if virtualizable, multiplied UUTs may be tested simultaneously according to different requirements, and the testing may be executed on shared hardware in a manner transparent to the UUTs.

A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack, and wherein each DUT in the array of DUTs aligns with a respective socket of the plurality of sockets on the interface board. The testing apparatus further comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.

Various embodiments of the invention provide a system and a method for testing one or more devices under test (DUTs) and for checking one or more test setups. Each of the one or more test setups includes a test board having several sockets for receipt of a DUT. A custom hardware interface is used to electrically connect the test board, such as a burn-in board with a test system configuration having multiple modules that can be configured using a computer device and related software to provide customized testing of the DUTs. The system is scalable to accommodate any DUT having any number of channels and to provide customized testing. Results of the testing are sent to the computing device.

One example includes a battery power system that includes a plurality of battery containers. Each of the battery containers can include a plurality of battery modules that provide output power to a point-of-interconnect associated with a power grid. Each of a portion of the plurality of battery containers includes a plurality of original battery modules and at least one of a plurality of redistributed battery modules from a redistributed battery container. The redistributed battery container includes battery modules of a substantially similar state-of-health to the plurality of original battery modules of each of the portion of the plurality of battery containers. The redistributed battery container includes a plurality of newer battery modules with a substantially similar state-of-health that is greater than the state-of-health of the plurality of original battery modules and which were subsequently installed after redistribution of the plurality of redistributed battery modules.

A virtualizable automated test equipment architecture includes a circuit assembly. The circuit assembly includes a number of signal paths that extend between a front plane and a backplane. The signal paths can be continuous and isolated from other signal paths of the plurality of signal paths. The circuit assembly also includes an impedance disposed along a signal path of the plurality of signal paths. A plurality of software-configurable physical disconnects may be arranged within the circuit assembly to form a switching matrix. The plurality of signal paths can be associated with a plurality of software-configurable physical disconnects, which can be configured to open and close signal paths of the plurality of signal paths based on the predetermined test requirements. The circuit assembly also includes a plurality of external device connections, at least one of which may be configured to interface with a unit under test (UUT). The software configurable physical disconnects may be configurable at runtime. Because the system if virtualizable, multiplied UUTs may be tested simultaneously according to different requirements, and the testing may be executed on shared hardware in a manner transparent to the UUTs.

A waveform data acquisition module includes an A/D converter that converts an electrical signal relating to a DUT into a digital signal, and a first memory unit that stores waveform data configured as a digital signal sequence. A function test module includes a test unit and a second memory unit. A higher-level controller instructs the waveform data acquisition module to start data sampling, and holds the time point thereof. Furthermore, the higher-level controller instructs the function test module to start to execute a pattern program, and records the time point thereof. The first memory unit records the time point at which the data sampling is started. The higher-level controller records the time point at which the execution of the pattern program is started.

A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack, and wherein each DUT in the array of DUTs aligns with a respective socket of the plurality of sockets on the interface board. The testing apparatus further comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.

An automated test equipment comprises a main test flow control configured to operate a test flow in multiple device communication units and/or to provide the trigger configuration information to a local compute unit. The automated test equipment further comprises a device communication unit comprising a trigger generation unit configured to generate a trigger signal. The trigger generation unit further configured to extract payload data from a protocol-based data stream received from the device under test, and to generate the trigger signal in response to the extracted payload data or in response to one or more protocol events. A method and a computer program for testing one or more devices under test in an automated test equipment are also disclosed.

A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack, and wherein each DUT in the array of DUTs aligns with a respective socket of the plurality of sockets on the interface board. The testing apparatus further comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.

A system and method are disclosed for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.