A chip testing apparatus and system suitable for performing testing on multiple chips in a chip cluster are provided. The chip testing apparatus includes a signal interface and a test design circuit. The signal interface transmits an input signal and multiple driving signals in parallel from a test equipment to each of the chips. The test design circuit receives multiple output signals from the chips through the signal interface and serially outputs a test data to the test equipment according to the output signals.

A test arrangement for adjusting a setup of testing a device under test (DUT) includes a main device that generates an RF signal and processes an incoming RF signal in a first frequency range; a frontend component generates an RF signal and processes an incoming RF signal in a second frequency range. The frontend component measures a signal level in a sub-range within the first frequency range; a connection cable connects the main device with the frontend component; and an analyzer predicts a behavior of the connection cable in a rest portion of the first frequency range that is different from the sub-range within the first frequency range.

A system and method are disclosed for assembling a testbench for evaluating electronic systems. The method includes assembling large testbenches by using verification features associated with functional components, automatically creating component connections, and statistically checking the testbench prior to generation and simulation. The system includes a computer system that implements the method.

Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.

The present disclosure provides a method of testing a single device under test (DUT) through multiple cores in parallel, which includes steps as follows. The test quantity of the DUT is calculated; the test quantity of the DUT is evenly allocated to to a plurality of test cores, so as to control a period of testing the DUT through the test cores in parallel.

A personal laboratory includes a self-contained, miniaturized, portable kit that provides for design, testing, and automated assembling, dissembling, and reassembling of a physical system (rather than a simulation) with flexibility as to the variety of configurations of components that may be designed and assembled, and easy integration of complex components. The personal laboratory includes a reconfigurable system, the reconfigurable system includes a plurality of functional components, and a plurality of connectors configured for operatively connect respective functional components to other functional components; a stimulus generator configured to apply a stimulus to the reconfigurable system; and a measurement system configured to measure a response to the applied stimulus generated by the reconfigurable system. In the context of electronic circuits, the reconfigurable system is a reconfigurable circuit, the functional components are circuit elements and the connectors are electrical connectors.

A cartridge, including a cartridge frame, formations on the cartridge frame for mounting the cartridge frame in a fixed position to an apparatus frame, a contactor support structure, a contactor interface on the contactor support structure, a plurality of terminals, held by the contactor support structure, for contacting contacts on a device, and a plurality of conductors, held by the contactor support structure, connecting the interface to the terminals.

On-chip field testing methods and apparatus are disclosed. Example on-chip testers disclosed herein include a decoder having a test data input and a test stimuli interface. Disclosed example on-chip testers also include a multiplexer having a first multiplexer interface coupled to the test stimuli interface, a second multiplexer interface coupled to an automatic test equipment interface, a third multiplexer interface coupled to a design-for-testing subsystem interface and an interface selection input. Disclosed example on-chip testers further include a memory having a memory interface coupled to the test data input.

An apparatus for performing multiple tests on a device under test (DUT) are provided. The apparatus includes at least one non-transitory computer-readable medium having stored thereon computer-executable instructions and at least one processor coupled to the at least one non-transitory computer-readable medium. The computer-executable instructions are executable by the at least one processor and cause the apparatus to perform operations of inputting a plurality of test patterns to a test apparatus, performing each of the plurality of test patterns on the DUT without interruption, and obtaining a respective result for the DUT in response to each of the plurality of test patterns.

The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYs (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.