A system for over-the-air testing of a device under test includes a measurement antenna, a reference antenna, a device under test capable of wirelessly transmitting and/or receiving complex radio frequency signals, and an analyzer. The analyzer has at least two ports, wherein the reference antenna is connected with a first port of the analyzer. The measurement antenna is connected with a second port of the analyzer. The analyzer is capable of determining a phase difference and a power ratio of radio frequency signals received via the measurement antenna and the reference antenna. The analyzer is capable of performing an IQ analysis on complex radio frequency signals. Further, a method of over-the-air testing of a device under test is disclosed.

A cartridge, including a cartridge frame, formations on the cartridge frame for mounting the cartridge frame in a fixed position to an apparatus frame, a contactor support structure, a contactor interface on the contactor support structure, a plurality of terminals, held by the contactor support structure, for contacting contacts on a device, and a plurality of conductors, held by the contactor support structure, connecting the interface to the terminals.

Example automatic test equipment (ATE) includes a first test instrument to receive a waveform from a device under test, where the waveform is based on test signals sent from the ATE to the DUT; circuitry to generate digital pulses based on the waveform; and a second test instrument to receive the digital pulses over at least two digital pins and to process the digital pulses to test the DUT.

Embodiments of the present invention provide systems and methods for performing device testing using automatic test equipment that can advantageously utilize relatively large numbers of test scenarios and activities including multiple test steps and resources and that prevents test parameters from conflicting or colliding to improve test performance and accuracy. The test activities of a given test scenario can be configured to be executed concurrently. The test activities can be associated with one or more test parameters characterized by respective test parameter values and/or are associated with one or more constraints

An automated test equipment for testing one or more devices under test comprising a plurality of port processing units, comprising at least a respective buffer memory, and a respective high-speed-input-output, HSIO, interface for connecting with at least one of the devices under test. The port processing units are configured to receive data, store the received data in the respective buffer memory, and provide the data stored in the respective buffer memory to one or more of the connected devices under test via the respective HSIO interface for testing the one or more connected devices under test. A method and computer program for automated testing of one or more devices under test are also described.

An automated test equipment for testing a device under test comprises an on-chip-system-test controller. The on-chip system test controller comprises at least one debug interface or control interface configured to communicate with the device under test. The on-chip-system-test controller optionally comprises at least one high bandwidth interface configured to communicate with the device under test. The on-chip-system-test controller is configured to control a test of a device-under-test which is a system-on-a chip.

An example test system includes power amplifier circuitry to force voltage or current to a test channel and one or more processing devices configured to control the power amplifier circuitry to comply with a compliance curve. The compliance curve relates output of the voltage to output of the current. According to the compliance curve, maximum current output increases as an absolute value of the voltage output increases.

A device of a data testing environment including a node configured to connect the device to a tester; one or more processors configured to receive from the node an electrical signal alternating between at least a first state and a second state, the first state representing a data transmission trigger and the second state representing a data transmission opportunity; determine a timing of the data transmission opportunity based on the received electrical signal; and send data to the node during the data transmission opportunity in response to receiving the data transmission trigger.

A signal processing method is provided. The signal processing method is used in a Gigabit Ethernet system including a device under test (DUT) and a link partner (LP), and includes the following steps. Firstly, an interference detector is configured to detect whether the Gigabit Ethernet system is interfered by other signal sources. Next, a physical layer (PHY) of the DUT or a PHY of the LP is used to, in response to the Gigabit Ethernet system being interfered by the other signal sources, set a request signal indicating whether or not the physical layer enters a low power idle (LPI) mode as FALSE. Which PHY of the DUT and the LP is used to set the request signal indicating whether or not the PHY enters the LPI mode as FALSE depends upon which one of the DUT and the LP is provided with the interference detector.

The present invention provides an improved testing of a complex device under test, in particular a parallel analysis of signals of a device under test. Multiple signals of the device under test may be acquired and characteristic parameters of the acquired signals may be determined. The determined characteristic parameters of the multiple signals may be stored. In particular, the characteristic parameters may be stored in form of an array, table or spread sheet.