A chip testing circuit and a testing method thereof are provided. The chip testing circuit includes a parameter measurement circuit, a plurality of power supply circuits, a plurality of switch circuits, and a control circuit. The plurality of power supply circuits respectively provide power supply to a plurality of chips carried by a plurality of sockets. Each switch circuit is electrically connected between one socket and one power supply circuit. The control circuit is connected in parallel to a plurality of signal pins of the plurality of chips carried by the plurality of sockets, so that when the control circuit outputs test data, all the chips can simultaneously receive the test data. When executing a parametric test mode, the control circuit controls one of the switch circuits to be turned on and controls the parameter measurement circuit to perform an electrical performance test on the chips.

A chip testing circuit and a testing method thereof are provided. The chip testing circuit includes a parameter measurement circuit, a plurality of power supply circuits, a plurality of switch circuits, and a control circuit. The plurality of power supply circuits respectively provide power supply to a plurality of chips carried by a plurality of sockets. Each switch circuit is electrically connected between one socket and one power supply circuit. The control circuit is connected in parallel to a plurality of signal pins of the plurality of chips carried by the plurality of sockets, so that when the control circuit outputs test data, all the chips can simultaneously receive the test data. When executing a parametric test mode, the control circuit controls one of the switch circuits to be turned on and controls the parameter measurement circuit to perform an electrical performance test on the chips.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. Presented embodiments enable efficient and effective random generation of test input information. In one embodiment a method includes accessing a plurality of data values to write to a DUT, generating a plurality of addresses pseudo randomly and assigning the address to a respective one of the data values, wherein assignments of a particular address to different respective ones of the data values are randomly repeatable; and directing writing of the data values to the DUT in accordance with the plurality of addresses that are randomly generated and randomly repeated. The generating a plurality of addresses randomly can include normalization. Generating a plurality of addresses pseudo randomly and assigning the address to a respective one of the data values can include performing a confirmation check. The confirmation check can include checking if the addresses within proper parameters.

A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.

An automated test equipment (ATE) system capable of performing a test of semiconductor devices is presented. The system comprises a first test board including a first FPGA communicatively coupled to a controller via an interface board, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a DUT. The system also includes a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a device under test, wherein the second FPGA is further programmed to simulate a DUT, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.

An automated test equipment (ATE) system comprises a system controller communicatively coupled to a tester processor, where the system controller is operable to transmit instructions to the tester processor, and where the tester processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The apparatus also comprises an FPGA programmed to support a first protocol communicatively coupled to the tester processor comprising at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing a DUT of the plurality of DUTs. Further, the apparatus comprises a bus adapter comprising a protocol converter module operable to convert signals associated with the first protocol received from the FPGA to signals associated with a second protocol prior to transmitting the signals to the DUT, wherein the DUT communicates using the second protocol.

The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.

An automated test equipment for testing one or more devices under test comprising a plurality of port processing units, comprising at least a respective buffer memory, and a respective high-speed-input-output, HSIO, interface for connecting with at least one of the devices under test. The port processing units are configured to receive data, store the received data in the respective buffer memory, and provide the data stored in the respective buffer memory to one or more of the connected devices under test via the respective HSIO interface for testing the one or more connected devices under test. A method and computer program for automated testing of one or more devices under test are also described.

An automated test equipment for testing one or more devices under test, comprises at least one port processing unit, comprising a high-speed-input-output interface, HSIO, for connecting with at least one of the devices under test, a memory for storing data received by the port processing unit from one or more connected devices under test, and a streaming error detection block, configured to detect a command error in the received data, wherein the port processing unit is configured to, in response to detection of the command error, limit the storing in the memory of data following, in the received data, after the command which is detected to be erroneous. A method and computer program for automated testing of one or more devices under test are also described.

In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.