On-chip spread spectrum characterization including obtaining, from a skitter circuit, skitter data comprising a spread width corresponding to an amplitude of a spread of a spread spectrum clock signal; setting an offset pointer to a center of the spread width corresponding to the amplitude of the spread; retrieving, for each of a number of reference clock cycles, edge data indicating a location, within the spread width, of an edge of the spread spectrum during the reference clock cycle; incrementing, using the edge data, an offset counter for each reference clock cycle during which the edge of the spread spectrum crosses the offset pointer; and calculating a frequency of the spread spectrum using the offset counter and the number of reference clock cycles.

A multi-channel timing calibration device and a method applicable thereto are provided. The device includes: a plurality of channel inputs, at least one relay switch, at least one comparator, at least one first multiplexer, and a time measurement chip. The at least one comparator is connected to the at least one relay switch, and connected to a reference voltage or a digital analog converter. The at least one first multiplexer has different signals for different channel groups and outputs a signal of a designated channel. The time measurement chip calculates a timing difference of each of the channels of each of the channel inputs as a basis for delay of the timing signals.

A chip test device and a chip test method are provided. The chip test device may include a chip socket and an interface card comprising a signal synthesizer, a plurality of first interfaces and a second interface. The signal synthesizer may be configured to synthesize a plurality of low-frequency first signals output from a plurality of testers into a high-frequency second signal and transmit the second signal to the chip socket. The plurality of first interfaces may be arranged in a plurality of inputs of the signal synthesizer for connecting the testers, and the second interface may be arranged in an output of the signal synthesizer for connecting the chip socket. By synthesizing the low-frequency first signals into the high-frequency second signal, a high-frequency test may be conducted using a plurality of low-frequency testers.

A device of a data testing environment including a node configured to connect the device to a tester; one or more processors configured to receive from the node an electrical signal alternating between at least a first state and a second state, the first state representing a data transmission trigger and the second state representing a data transmission opportunity; determine a timing of the data transmission opportunity based on the received electrical signal; and send data to the node during the data transmission opportunity in response to receiving the data transmission trigger.

A circuit configured to: generate a reference clock signal; generate an excitation signal at a target frequency having a period that is a first integer number of cycles of the reference clock signal; update a driver circuit at an update frequency having a period that is a second integer number of cycles of the reference clock signal; digitize sense signals resulting from the excitation signal at a frequency having a period that is a third integer number of cycles of the reference clock signal; identify a fourth integer number of sense signal samples; optionally utilize an excitation control signal having a period that is a fifth integer number of cycles of the reference clock signal; and minimize harmonics at the target frequency of the excitation signal based on the first integer number, the second integer number, the third integer number, the fourth integer number, and possibly the fifth integer number.

A deskew system can be used to adjust signal characteristics such as pulse width and edge timing. In an example, a deskew system can include multiple timing control cells and each cell can operate in one of multiple different modes according to respective mode control signals. The modes can include at least a signal delay mode and a signal pulse width adjustment mode. In an example, a first cell in a deskew system can be configured to receive a test input signal at a first input node and, in response, provide a deskew output signal at a first output node. The deskew output signal can be based on the test input signal, a pulse width adjustment provided by the first cell, and on a delayed signal, corresponding to the input signal, that is provided by a subsequent cell in the series.

A deskew system can be used to adjust signal characteristics such as pulse width and edge timing. In an example, a deskew system can include multiple timing control cells and each cell can operate in one of multiple different modes according to respective mode control signals. The modes can include at least a signal delay mode and a signal pulse width adjustment mode. In an example, a first cell in a deskew system can be configured to receive a test input signal at a first input node and, in response, provide a deskew output signal at a first output node. The deskew output signal can be based on the test input signal, a pulse width adjustment provided by the first cell, and on a delayed signal, corresponding to the input signal, that is provided by a subsequent cell in the series.

A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.

A testing device and a method for testing a device under test are provided. The testing device comprises at least two signal generators, at least two numerically controlled oscillators, at least two white gaussian noise generators, at least two digital filters, each of which comprising a respective transfer function H.sub.i, at least two adders, at least two digital-to-analog converters, and an analog processor.

A self-test mechanism within an integrated circuit to test for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism intentionally injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of an artificially generated, imaginary specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the artificially generated, imaginary specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.